Patents Examined by Toan K Le
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Patent number: 11322203Abstract: A system that includes a non-volatile memory subsystem having non-volatile memory. The system also includes a plurality of memory modules that are separate from the non-volatile memory subsystem. Each memory module can include a plurality of random access memory packages where each first random access memory package includes a primary data port and a backup data port. Each memory module can include a storage interface circuit coupled to the backup data ports of the random access memory packages. The storage interface circuit offloads data from the memory module in the event of a power loss by receiving data from the backup data ports of the random access memory packages and transmitting the data to the non-volatile memory subsystem.Type: GrantFiled: October 8, 2020Date of Patent: May 3, 2022Assignee: Rambus Inc.Inventors: Aws Shallal, Nigel Alvares, Sarvagya Kochak
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Patent number: 11322194Abstract: Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.Type: GrantFiled: January 13, 2021Date of Patent: May 3, 2022Assignee: Micron Technology, Inc.Inventors: Minoru Someya, Yukihide Suzuki, Sadayuki Okuma
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Patent number: 11276464Abstract: A method, includes: applying a read voltage at a first read voltage level to read a memory cell for detecting a resistance level of the memory cell; applying the read voltage at a second read voltage level, different from the first read voltage level, to read the memory cell for determining a waveform type has been utilized to program the memory cell; recognizing data bits stored in the memory cell. The data bits stored in the memory cell comprise a first data bit and at least one second data bit. The first data bit is recognized according to the waveform type and is irrelevant with the resistance level. The at least one second data bit is recognized according to the resistance level and is irrelevant with the waveform type. A device is also disclosed herein.Type: GrantFiled: October 23, 2020Date of Patent: March 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jau-Yi Wu, Yu-Sheng Chen
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Patent number: 11276474Abstract: A storage device includes a non-volatile memory including a plurality of blocks, a buffer memory, and a controller that stores an on-cell count in the buffer memory, the on-cell count indicating a number of memory cells, which are turned on by a read level applied to a reference word line of each of the plurality of blocks, from among memory cells connected to the reference word line.Type: GrantFiled: December 7, 2020Date of Patent: March 15, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Hyunkyo Oh, Sangkwon Moon
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Patent number: 11264071Abstract: A magnetoresistance effect element where asymmetry of an inversion current due to a leakage magnetic field from a magnetization fixed layer is decreased. A magnetoresistance effect element includes a first ferromagnetic layer whose magnetization direction is variable, a second ferromagnetic layer whose magnetization direction is fixed, and a nonmagnetic layer sandwiched between the first ferromagnetic layer and the second ferromagnetic layer which are laminated in a first direction which is a lamination direction, where both the first ferromagnetic layer and the second ferromagnetic layer are curved so that central portions of the first and second ferromagnetic layers protrude with respect to outer circumferential portions in the first direction, and protruding directions of the central portions are opposite to each other so that a distance between the outer circumferential portions is larger than a distance between the central portions in the first direction.Type: GrantFiled: June 26, 2020Date of Patent: March 1, 2022Assignee: TDK CORPORATIONInventor: Yohei Shiokawa
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Patent number: 11257533Abstract: A magnetic memory includes a storage element including a first ferromagnetic layer, a first conductive layer which faces the first ferromagnetic layer in a first direction and extends in a second direction different from the first direction, and a first conductive part and a second conductive part which are connected to the first conductive layer at positions which sandwich the first ferromagnetic layer in the second direction when seen in the first direction; and a plurality of first switching elements which are electrically connected to the first conductive part of the storage element.Type: GrantFiled: July 6, 2020Date of Patent: February 22, 2022Assignee: TDK CORPORATIONInventor: Yohei Shiokawa
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Patent number: 11250890Abstract: Memory devices and systems with configurable die powerup delay, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die has a powerup group terminal and powerup group detect circuitry. The powerup group detect circuitry is configured to detect a powerup group assigned to the at least one memory die. The at least one memory die is configured to delay its powerup operation by a time delay corresponding to the powerup group to which it is assigned. In this manner, powerup operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.Type: GrantFiled: February 23, 2021Date of Patent: February 15, 2022Assignee: Micron Technology, Inc.Inventors: Dale H. Hiscock, Michael Kaminski, Joshua E. Alzheimer, John H. Gentry
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Patent number: 11250915Abstract: According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.Type: GrantFiled: October 12, 2020Date of Patent: February 15, 2022Assignee: Toshiba Memory CorporationInventors: Hiroshi Maejima, Katsuaki Isobe, Naohito Morozumi, Go Shikata, Susumu Fujimura
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Patent number: 11244733Abstract: Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.Type: GrantFiled: November 15, 2019Date of Patent: February 8, 2022Assignee: Micron Technology, Inc.Inventors: Daniele Vimercati, Mark Fischer, Adam D. Johnson
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Patent number: 11238910Abstract: A signal generator includes N stages of cascaded control signal generating circuits, and is configured to receive K clock signals whose valid pulse edges are different from each other by a set time, an n-th control signal generating circuit of the N stages of control signal generating circuit generates a strobe signal based on a k-th clock signal of the K clock signals and sequentially outputs at least two different clock signals of other K?1 clock signals based on the strobe signal. A valid pulse edge of the k-th clock signal is within a valid pulse duration of a strobe signal of an (n?1)-th stage control signal generating circuit.Type: GrantFiled: March 30, 2020Date of Patent: February 1, 2022Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Junrui Zhang, Xuehui Zhu, Ronghua Lan, Zongze He, Yehao Zhang
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Patent number: 11238923Abstract: A memory device is provided. The memory device includes a cell array having a plurality of cells, each of the plurality of cells operative to store a bit value. The memory device further includes a reset circuit connected to the cell array. The reset circuit is operative to reset, in parallel, the bit value stored in each of the plurality of cells to a predetermined bit value.Type: GrantFiled: October 18, 2019Date of Patent: February 1, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventor: Shih-Lien Linus Lu
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Patent number: 11233192Abstract: A hall bar device for a memory or logic application can include a gate electrode, a boron-doped chromia layer on the gate electrode; and a hall bar structure with four legs on the boron-doped chromia layer. For a memory application, the hall bar device can be written to by applying a pulse voltage across the gate electrode and one leg of the hall bar structure in the absence of an applied magnetic field; and can be read from by measuring a voltage across the one leg of the hall bar structure and its opposite leg.Type: GrantFiled: August 7, 2020Date of Patent: January 25, 2022Assignee: BOARD OF REGENTS OF THE UNIVERSITY OF NEBRASKAInventors: Christian Binek, Ather Mahmood, William Echtenkamp
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Patent number: 11227657Abstract: A method of operating a semiconductor device, the semiconductor device includes: a memory block including a plurality of word lines; and a control logic for performing a first program operation on first memory cells corresponding to a first word line among the plurality of word lines, performing the first program operation on second memory cells corresponding to a second word line adjacent to the first word line, performing a second program operation on the first memory cells, performing a dummy program operation on third memory cells corresponding to a third word line adjacent to the second word line, and performing the second program operation on the second memory cells.Type: GrantFiled: September 14, 2020Date of Patent: January 18, 2022Assignee: SK hynix Inc.Inventor: Hee Youl Lee
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Patent number: 11189349Abstract: A memory device includes an erase operation controller for performing an erase operation on a memory block; an erase suspend count manager for managing an erase suspend count representing a number of times the erase operation is suspended until the erase operation on the memory block is completed; and a program parameter value determiner for determining a parameter value to be used for a program operation on the memory block, based on the erase suspend count.Type: GrantFiled: November 4, 2020Date of Patent: November 30, 2021Assignee: SK hynix Inc.Inventor: Se Chang Park
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Patent number: 11189333Abstract: A memory device includes a delay locked loop (DLL), a clock compensating circuit, and a data input/output (I/O) circuit. The DLL outputs a first clock signal and a second clock signal. The clock compensating circuit adjusts a voltage level of an output node and generates an inner clock signal based on the voltage level of the output node. The data I/O circuit outputs data to an outside based on the inner clock signal. The clock compensating circuit includes first and second pulse adjusting circuits. The first pulse adjusting circuit connected to a first output node and outputs a first adjusting current based on the first clock signal and a voltage level of the first output node. The second pulse adjusting circuit connected to a second output node and outputs a second adjusting current based on the second clock signal and a voltage level of the second output node.Type: GrantFiled: July 26, 2020Date of Patent: November 30, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang-Woo Ryu, Soojung Rho
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Patent number: 11164611Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In some embodiments, sense amplifier circuitry generates, based on an input signal at a first voltage level, an output signal at a second, different voltage level. Pulse circuitry may generate a pulse signal in response to an active clock edge of a clock signal that is input to the sense amplifier circuitry. Initial resolution circuitry may drive the output signal of the sense amplifier circuitry to match the value of the input signal during the pulse signal. Secondary resolution circuitry may maintain a current value of the output signal after expiration of the pulse signal. This may allow the input signal to change during the pulse, e.g., to enable time borrowing by upstream circuitry.Type: GrantFiled: June 19, 2020Date of Patent: November 2, 2021Assignee: Apple Inc.Inventors: Vivekanandan Venugopal, Ajay Bhatia
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Patent number: 11158364Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/?1) at a faster rate than counts for more distant victim rows (e.g., +/?2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.Type: GrantFiled: May 31, 2019Date of Patent: October 26, 2021Assignee: Micron Technology, Inc.Inventors: Daniel B. Penney, Jason M. Brown, Nathaniel J. Meier, Timothy B. Cowles, Jiyun Li
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Patent number: 11152044Abstract: A system for performing a phase matching operation includes a controller configured to output a dock, a command, and a strobe signal, and to input/output data. The system also includes a semiconductor device configured to generate an internal strobe signal by matching the phases of the command and the strobe signal according to the clock, and to input/output the data in synchronization with the internal strobe signal, wherein the semiconductor device generates the internal strobe signal from the strobe signal by compensating for a delay amount of a first path to which the command is inputted and a delay amount of a second path to which the strobe signal is inputted.Type: GrantFiled: July 17, 2020Date of Patent: October 19, 2021Assignee: SK hynix Inc.Inventors: Min Su Park, Min Gyu Park, Geun Ho Choi
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Patent number: 11152562Abstract: A non-volatile memory cell comprising: a storage layer comprised of a ferromagnetic or ferroelectric material in which data is recordable as a direction of magnetic or electric polarisation; a piezomagnetic layer comprised of an antiperovskite piezomagnetic material selectively having a first type of effect on the storage layer and a second type of effect on the storage layer dependent upon the magnetic state and strain in the piezomagnetic layer; and a strain inducing layer for inducing a strain in the piezomagnetic layer thereby to switch from the first type of effect to the second type of effect.Type: GrantFiled: December 6, 2017Date of Patent: October 19, 2021Assignee: IP2IPO Innovations LimitedInventors: Jan Zemen, Andrei Paul Mihai, Bin Zou, David Boldrin, Evgeniy Donchev
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Patent number: 11145366Abstract: Examples may include techniques to mitigate errors during a read operation to a memory cell of a memory array. Examples include selecting the memory cell and applying one of multiple demarcation read voltages for respective multiple time intervals to sense a state of a resistive storage element of the memory cell. Examples also include applying a bias voltage to the memory cell following a sense interval to mitigate read disturb to the resistive storage element incurred while the one of the multiple demarcation read voltages was applied to the memory cell.Type: GrantFiled: March 24, 2020Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Davide Mantegazza, Kiran Pangal