Patents Examined by Toan K Le
  • Patent number: 10797033
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for testing the resistance of through silicon vias (TSVs) which may be used, for example, to couple multiple memory dies of a semiconductor memory device. A force amplifier may selectively provide a known current along a mesh wiring structure and through the TSV to be tested. The force amplifier may be positioned on a vacant area of the memory device, while the mesh wiring structure may be positioned in an area beneath the TSVs of the layers of the device. A chopper instrumentation amplifier may be selectively coupled to the TSV to be tested to amplify a voltage across the TSV generated by the current passing through the TSV. The chopper instrumentation amplifier may be capable of determining small resistance values of the TSV.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Akira Ide
  • Patent number: 10783932
    Abstract: To provide a magnetic memory for storing multi-level information capable of reading while sufficiently securing a read margin. Provided is a magnetic memory including: first and second magnetic storage elements that are provided between a first wiring and a second wiring crossing each other, and are electrically connected in series; a third wiring electrically connected between the first and second magnetic storage elements; a first determination unit that determines a magnetization state of the first magnetic storage element on the basis of a current flowing to the first magnetic storage element through the third wiring; and a second determination unit that determines a magnetization state of the second magnetic storage element on the basis of a current flowing to the first and second magnetic storage elements through the first wiring, in which the determination state of the second determination unit is changed on the basis of the determination result of the first determination unit.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 22, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Hiroyuki Uchida, Yo Sato, Naoki Hase
  • Patent number: 10777292
    Abstract: The present disclosure includes apparatuses and methods related to selectable trim settings on a memory device. An example apparatus can store a number of sets of trim settings and select a particular set of trims settings of the number of sets of trim settings based on desired operational characteristics for the array of memory cells.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • Patent number: 10770126
    Abstract: A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Richard E. Fackenthal
  • Patent number: 10770129
    Abstract: An embodiment of a semiconductor apparatus may include technology to provide two or more dynamic random access memory devices, and provide access to the two or more dynamic random access memory devices with two or more pseudo-channels per memory channel. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Hussein Alameer, Kjersten Criss, Uksong Kang
  • Patent number: 10762977
    Abstract: A memory storage device and a memory testing method for testing a memory array of the memory storage device are provided. The memory testing method includes the following steps: writing first data into a plurality of first segments of the memory array, and writing second data to a second segment of the memory array; obtaining third data by reading the plurality of first segments, and obtaining fourth data by reading the second segment; converting the fourth data to fifth data, wherein the fifth data is the same as check data obtained by encoding the first data by using an encoding circuit corresponding to a decoding circuit of the memory storage device.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 1, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Kuen-Huei Chang, Che-Min Lin
  • Patent number: 10755765
    Abstract: A layout structure of a bit line sense amplifier in a semiconductor memory device includes a first bit line sense amplifier which is connected to a first bit line and a first complementary bit line, and is controlled via a first control line and a second control line. The first control line is connected to a first node of the first bit line sense amplifier and the second control line is connected to a second node of the first bit line sense amplifier, and the first bit line sense amplifier includes at least one pair of transistors configured to share any one of a first active region corresponding to the first node and a second active region corresponding to the second node.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bok-Yeon Won, Hyuck-Joon Kwon
  • Patent number: 10748601
    Abstract: An integrated circuit chip includes: one or more couplers suitable for transferring data between stacked chips; one or more data nodes suitable for transferring data to a host; and one or more transfer circuits on a transfer path for transferring data between the one or more couplers and the one or more data nodes, wherein at least one transfer circuit among the one or more transfer circuits inverts a portion of the data which is transferred by the at least one transfer circuit.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: August 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Ji-Hwan Kim, Heat-Bit Park
  • Patent number: 10741254
    Abstract: A memory system includes a memory device suitable for storing an erase count list where a first erase count of each of a plurality of memory blocks is recorded, and a controller suitable for counting the first erase count of each of the memory blocks, updating the erase count list to reflect the first erase count, selecting victim blocks from the memory blocks, checking a second erase count corresponding to each of the victim blocks, updating a victim block erase count list to reflect the second erase count, comparing the first erase count and the second erase count which correspond to a target victim block, among the victim blocks, and moving data stored in the target victim block to a normal block when the first erase count is equal to the second erase count.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 11, 2020
    Assignee: SK hynix Inc.
    Inventor: Jin-Pyo Kim
  • Patent number: 10734084
    Abstract: A non-volatile storage system comprises non-volatile memory cells arranged in physical blocks, and one or more control circuits in communication with the non-volatile memory cells. The one or more control circuits are configured to write data to a physical block of the non-volatile memory cells with a scheme to reduce read disturb if a logical block associated with the physical block has a read intensity greater than a threshold.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: August 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Narayan Kuddannavar, Swaroop Kaza, Sainath Viswasarai
  • Patent number: 10734040
    Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In some embodiments, sense amplifier circuitry generates, based on an input signal at a first voltage level, an output signal at a second, different voltage level. Pulse circuitry may generate a pulse signal in response to an active clock edge of a clock signal that is input to the sense amplifier circuitry. Initial resolution circuitry may drive the output signal of the sense amplifier circuitry to match the value of the input signal during the pulse signal. Secondary resolution circuitry may maintain a current value of the output signal after expiration of the pulse signal. This may allow the input signal to change during the pulse, e.g., to enable time borrowing by upstream circuitry.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 4, 2020
    Assignee: Apple Inc.
    Inventors: Vivekanandan Venugopal, Ajay Bhatia
  • Patent number: 10734079
    Abstract: The disclosure relates in some aspects to a read scrub design for a non-volatile memory that includes a block comprising N wordlines partitioned into a first sub-block comprising a first subset of the N wordlines and a second sub-block comprising a second subset of the N wordlines different than the first subset. In some aspects, the disclosure relates to detecting a trigger event associated with a read command performed on the first sub-block. A target sub-block test is then performed in response to a detection of the trigger event to determine whether to add the first sub-block to a read scrub queue. If the first sub-block is added to the read scrub queue, a sister sub-block test is then performed to determine whether to add the second sub-block to the read scrub queue.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Srinivasan Seetharaman, Sourabh Sankule, Piyush Girish Sagdeo, Gautam Ashok Dusija, Chris Nga Yee Yip
  • Patent number: 10727404
    Abstract: A tunable resistive element includes a first terminal, a second terminal and a resistive layer having a tunable resistive material. The resistive layer is arranged between the first terminal and the second terminal. The resistive element further includes a piezoelectric layer having a piezoelectric material. The piezoelectric layer is adapted to apply stress to the resistive layer. An electrical resistance of the tunable resistive material is dependent upon a first electrical control signal applied to the first terminal and the second terminal as well as upon the stress applied by the piezoelectric layer to the resistive layer. The stress applied by the piezoelectric layer is dependent on a second electrical control signal applied to the piezoelectric layer.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jean Fompeyrine, Youri Popoff, Stefan Abel
  • Patent number: 10720194
    Abstract: In a semiconductor memory device, a memory cell array includes a plurality of memory cells. A write circuit includes a negative potential generating circuit that generates a potential lower than a lower power supply potential applied to the memory cells. When a write mask signal indicates an enabled state, the write circuit activates the negative potential generating circuit, and supplies the potential generated by the negative potential generating circuit to a bit line to be supplied with low data. On the other hand, when the write mask signal indicates a disabled state, the write circuit supplies no data to bit line pairs, and inactivates the negative potential generating circuit.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: July 21, 2020
    Assignee: SOCIONEXT INC.
    Inventor: Yoshinobu Yamagami
  • Patent number: 10714189
    Abstract: A method of verifying the atomicity of an operation of data update in an EEPROM, includes, during a data writing operation of writing the data, the steps of: initializing at least one first flag to a first value and storing this value in the EEPROM; erasing the data from the EEPROM; writing a value of the data into the EEPROM; and writing at least one second value of the first flag into the EEPROM.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: July 14, 2020
    Assignee: PROTON WORLD INTERNATIONAL N.V.
    Inventors: Guillaume Docquier, Ronny Van Keer
  • Patent number: 10714202
    Abstract: A magnetic memory included a conductive line that extends in a first direction along a substrate. A first columnar body is in a memory cell array region of the substrate and extends in a second direction from the substrate. A first end of the first columnar body contacts the conductive line. The first columnar body is comprised of a first magnetic material and has magnetic domains adjacent to one another along a length of the first columnar body in the second direction. A second columnar body is in a peripheral region of the substrate and extending in the second direction from the substrate. A first end of the second columnar body contacts the conductive line, and a second end is connected to a control circuit. The second columnar body also is comprised of the first magnetic material.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: July 14, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshihiro Ueda
  • Patent number: 10706917
    Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Yuichiro Ishii, Yohei Sawada, Makoto Yabuuchi
  • Patent number: 10706914
    Abstract: A static random access memory (SRAM) structure includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, a second inverter comprising a second pull-up transistor and a second pull-down transistor, a first pass transistor coupled to the first inverter, and a second pass transistor coupled to the second inverter. Preferably, the first inverter is coupled to a first tunnel magnetoresistance (TMR) structure and the second inverter is coupled to a second TMR structure.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ching-Cheng Lung, Yu-Tse Kuo, Chun-Hsien Huang, Hsin-Chih Yu, Shu-Ru Wang
  • Patent number: 10692553
    Abstract: An integrated circuit includes: a delay circuit suitable for delaying one or more input signals; a toggle sensing circuit suitable for sensing whether or not the one or more input signals toggle; and a replica delay circuit suitable for delaying one or more clock signals in a section where no toggle of the one or more input signals is sensed by the toggle sensing circuit.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: June 23, 2020
    Assignee: SK hynix Inc.
    Inventor: Ja-Young Kim
  • Patent number: 10685688
    Abstract: Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Muhammad M. Khellah