Abstract: A first film having a repetitive line pattern is formed on an under film. A second film is formed on a side surface of the first film. The second film has an etching selectivity different from that of the first film. A third film is formed on an upper surface and a side surface of the second film. The third film has an etching selectivity different from those of the first and second films. A resist pattern with an opening is formed on the third film. A recess that exposes upper surfaces of the first, second and third films is formed by etching the third film by using the resist pattern as an etching mask. An upper surface of the under film is exposed by etching the first and third films. A through hole that penetrates through the under film is formed by etching the under film.

Abstract: A method of fabricating a packaging substrate includes following steps: providing a carrier board having two opposite surfaces, forming on each of the surfaces a plurality of first metal bumps; covering the carrier board and the first metal bumps with a first dielectric layer that has a plurality of first intaglios which exposes a top surface and side surface of the first metal bumps; forming a conductive seedlayer on the first dielectric layer and the first metal bumps; forming a metal layer on the conductive seedlayer; removing a portion of the metal layer and the conductive seedlayer that is higher than the top surface of the first dielectric layer, and forming a first circuit layer in the first intaglios; forming a built-up structure on the first circuit layer and the first dielectric layer, forming a pair of upper and lower entire packaging substrates.

Abstract: A base insulating film is formed over a substrate. A first oxide semiconductor film is formed over the base insulating film, and then first heat treatment is performed to form a second oxide semiconductor film. Then, selective etching is performed to form a third oxide semiconductor film. An insulating film is formed over the first insulating film and the third oxide semiconductor film. A surface of the insulating film is polished to expose a surface of the third oxide semiconductor film, so that a sidewall insulating film is formed in contact with at least a side surface of the third oxide semiconductor film. Then, a source electrode and a drain electrode are formed over the sidewall insulating film and the third oxide semiconductor film. A gate insulating film and a gate electrode are formed.

Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.

Abstract: Provided is a device with improved reverse-recovery immunity of a diode element. The device includes: a first conductivity-type drift layer; a second conductivity-type anode region provided in an upper portion of the drift layer; a second conductivity-type extraction region in contact with and surrounding the anode region; and a second conductivity-type field limiting ring region surrounding and separated from the extraction region at the upper portion of the drift layer, wherein the extraction region has a greater depth than the anode region and the field limiting ring region.

Abstract: In the case where a signal delay is found in a circuit operation in a semiconductor chip, when a repeater for delay reduction is additionally formed as a result of a design change, an increase in the area of the semiconductor chip and an increase in the manufacturing cost of a semiconductor device are prevented. The inverter forming the repeater is formed of transistors formed in the upper portion of stacked wiring layers, not transistors in the vicinity of a main surface of a semiconductor substrate. By thus implementing a design change such that the repeater is added, the number of the wiring layers which need a layout change is reduced.

Abstract: A method includes forming a first polysilicon structure over a first portion of a substrate. A second polysilicon structure is formed over a second portion of the substrate. Two spacers are formed on opposite sidewalls of the second polysilicon structure. A layer of protective material is formed to cover the first and second portions of the substrate. The layer of protective material has a first thickness over the second polysilicon structure and a second thickness over the two spacers. The first thickness is equal to or greater than 500 ?, and the second thickness is equal to or less than 110% of the first thickness. A patterned photo resist layer is formed to cover a first portion of the layer of protective material that covers the first portion of the substrate. The second portion of the layer of protective material is removed.

Abstract: A method is provided. The method includes providing a first wafer having a plurality of first dummy pads exposed along a first surface of the first wafer. The first dummy pads contact a first metallization layer of the first water. The method also includes providing a second wafer having a plurality of second dummy pads exposed along a first surface of the second wafer. The second dummy pads contact a second metallization layer of the second wafer. The method also includes bonding the first wafer to the second wafer in a manner that the first surface of the first wafer contacts the first surface of the second wafer and the plurality of first dummy pads are interleaved with the plurality of second dummy pads but do not contact the plurality of second dummy pads.

Abstract: A thin film transistor (TFT), a method for fabricating the same, an array substrate and a display device are provided. The TFT includes a source electrode and a drain electrode, a semiconductor active layer, a gate insulating layer and a gate electrode. The TFT further includes a light-shielding layer between the source electrode and the drain electrode. The light-shielding layer separates the source electrode and the drain electrode, and the light-shielding layer is disposed on a light incident side of the semiconductor active layer and is used to prevent the incident light from irradiating on the semiconductor active layer.

Abstract: A substrate having an insulating surface is prepared; a stacked film including a first oxide semiconductor layer and a second oxide semiconductor layer is formed over the substrate; a mask layer is formed over part of the stacked film and then dry etching treatment is performed, so that the stacked film is removed, with a region provided with the mask layer remaining, and a reaction product is formed on a side surface of the remaining stacked film; the reaction product is removed by wet etching treatment after removal of the mask layer; a source electrode and a drain electrode are formed over the stacked film; and a third oxide semiconductor layer, a gate insulating film, and a gate electrode are stacked and formed in this order over the stacked film, and the source electrode and the drain electrode.

Abstract: In one embodiment, an IC package assembly for a switching regulator, can include: a power switch chip including a control electrode and a first electrode on an obverse side and a second electrode on a reverse side, where the second electrode is configured as a switching terminal of a switching regulator; a control chip including a driving electrode and a plurality of input and output electrodes on the obverse side; and a leadframe including an extension pin, a substrate, and a plurality of discrete pins, where the extension pin is formed integrally with the substrate, and where the reverse side of the power switch chip is arranged on the substrate of the leadframe by a conductive material to electrically connect the second electrode to the substrate.

Abstract: A photodiode according to example embodiments includes an anode, a cathode, and an intrinsic layer between the anode and the cathode. The intrinsic layer includes a P-type semiconductor and an N-type semiconductor, and composition ratios of the P-type semiconductor and the N-type semiconductor vary within the intrinsic layer depending on a distance of the intrinsic layer from one of the anode and the cathode.

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

Abstract: One illustrative method disclosed includes, among other things, forming an initial conductive source/drain structure that is conductively coupled to a source/drain region of a transistor device, performing a recess etching process on the initial conductive source/drain structure to thereby define a stepped conductive source/drain structure with a cavity defined therein, forming a non-conductive structure in the cavity, forming a layer of insulating material above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, forming a gate contact opening in the layer of insulating material and forming a conductive gate contact in the gate contact opening that is conductively coupled to the gate structure.

Abstract: An organic light-emitting device including a first electrode, a second electrode facing the first electrode, and an organic layer between the first electrode and the second electrode and including an emission layer, wherein the organic layer includes a first compound and a second compound; the first compound is represented by one selected from Formulae 1-1 to 1-4, and does not include a nitrogen-containing heterocyclic group that includes *?N—*? as a ring-forming moiety, and the second compound is represented by Formula 2:

Abstract: In an embodiment, an electronic component includes a dielectric core layer having a thickness, at least one semiconductor die embedded in the dielectric core layer and electrically coupled to at least one contact pad arranged on a first side of the dielectric core layer, and a heat dissipation layer arranged on a second side of the dielectric core layer and thermally coupled to the semiconductor die. The semiconductor die has a thickness that is substantially equal to, or greater than, or equal to the thickness of the dielectric core layer. The heat dissipation layer includes a material with a substantially isotropic thermal conductivity.

Abstract: According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the first interconnects. In the second region, the first interconnect group includes a step portion. Heights of adjacent terraces of the step portion are different from each other by the two or more first interconnects.

Abstract: An integrated circuit and method having a first PMOS transistor with extension and pocket implants and with SiGe source and drains and having a second PMOS transistor without extension and without pocket implants and with SiGe source and drains. The distance from the SiGe source and drains to the gate of the first PMOS transistor is greater than the distance from the SiGe source and drains to the gate of the second PMOS transistor and the turn on voltage of the first PMOS transistor is at least 50 mV higher than the turn on voltage of the second PMOS transistor.

Abstract: A semiconductor die comprises two or more active regions over a substrate. A first set of dummy blocks are over the substrate, in contact with one another, and completely surrounding at least one of the two or more active regions. A second set of dummy blocks are over the substrate and farther from the at least one active region surrounded by the first set of dummy blocks than the dummy blocks of the first set of dummy blocks. Each of the dummy blocks of the first set of dummy blocks has individual surface areas, each of the dummy blocks of the second set of dummy blocks has individual surface areas, and the individual surface areas of each of the dummy blocks of the second set of dummy blocks is larger than the individual surface areas of each of the dummy blocks of the first set of dummy blocks.

Abstract: A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.