Abstract: An apparatus and method for use in a semiconductor memory device to detect dataline undershoot. The detection of dataline undershoot is used to reduce dataline recovery time and output buffer recovery time, thereby reducing read access time in the memory device. A dataline coupled between a memory array and a sensing amplifier is applied to one input of a voltage comparator and compared to a reference voltage. The presence of undershoot on the dataline causes the dataline voltage to drop below the reference voltage, resulting in a transition in the comparator output. This transition triggers a pulse generator which supplies a pulse to the gate of a field effect transistor coupled between the dataline and an equalization voltage centered in a sensing window of the sensing amplifier.

Abstract: A P-channel MOS memory cell has P+ source and drain regions formed in an N-well. A thin tunnel oxide is provided between the well surface and an overlying floating gate. In one embodiment, the thin tunnel oxide extends over a substantial portion of the active region and the device. An overlying select and control gate is insulated from the floating gate by an insulating layer. The select and control gate including an elongated extension portion for preventing overprogramming of the circuit. The device is programmed via hot electron injection from the drain end of the channel region to the floating gate, without avalanche breakdown, which allows the cell to be bit-selectable during programming. Erasing is accomplished by electron tunneling from the floating gate to the N-well with the source, drain, and N-well regions equally biased. Since there is no high drain/well junction bias voltage, the channel length of the cell may be reduced without incurring and destructive junction stress.

Abstract: A circuit and method for generating an erasure voltage and a programming voltage for an EEPROM array, the cells of the EEPROM array being capable of erasure and programming. A signal having an increasing voltage is generated. That signal is monitored, and the increase in voltage of said signal is terminated when the signal reaches a first selected maximum level in an erase operation of at least one cell of the EEPROM array. In a program operation of at least one cell of the EEPROM array, the increase in voltage of the signal is terminated when said signal reaches a second selected maximum level.

Abstract: A serial dichotomic method for sensing multiple-level non-volatile memory cells which can take one of m=2.sup.n (n>=2) different programming levels, provides for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, and for: a) comparing the cell current with a reference current which has a value comprised between a minimum value and a maximum value of said plurality of m cell current values, thus dividing said plurality of cell current values into two sub-pluralities of cell current values, and determining the sub-plurality of cell current values to which the cell current belongs; b) repeating the step a) until the sub-plurality of cell current values to which the cell current belongs comprises only one cell current value, which is the value for the current of the memory cell to be sensed.

Abstract: A amplifier coupled to first and second power supply lines includes a first pair of cross-coupled transistors connected to the first power supply line and a pair of output terminals, and a second pair of cross-coupled transistors connected to the second power supply line. The amplifier includes a reset circuit which is provided between the first and second pairs of cross-coupled transistors and shortcircuits the pair of output terminals in response to a pair of predetermined control signals. The amplifier includes a pair of input transistors connected to the second pair of cross-coupled transistors, and a pair of non-linear elements which are provided between the first and second pairs of cross-coupled transistors.

Abstract: A semiconductor memory including at least one core block, each core block having sense amplifier arrays arranged alternately with memory cell arrays and sense amplifier drive circuits arranged at an end of the sense amplifier arrays. Additionally, a power source circuit is arranged in an L-shape along a long side and a short side of each core block. A power source wiring group is arranged in a mesh-like form above each core block for connecting the power source circuit to the sense amplifier drive circuits. As a result, sufficient power can be supplied to the circuits within the core block that require power, such as the sense amplifier drive circuits, without increasing chip area.

Abstract: An improved sense amplifier output control circuit of a semiconductor memory device increases the operational speed and reduces possible noise. A sense amplifier senses a data read from a memory cell in accordance with a sense enable signal applied thereto. A Schmitt trigger circuit outputs the same level signal when the level difference between a data signal outputted from the sense amplifier and a data bar signal inverted from the data signal is below a predetermined value, and outputs a different level signal when the level difference is increased more than a predetermined value. A data latch circuit inverts and outputs an output signal outputted from the Schmitt trigger circuit in accordance with a latch enable signal inputted thereto. A data output buffer outputs the same level signal as a data signal outputted from the sense amplifier when a signal outputted from the data latch circuit has a different level in accordance with an output enable signal inputted thereto.

Abstract: A device for reading memory cells, wherein the device contains two branches, wherein each branch comprises, connected in cascade, an electronic switch, an active element reactively connected to the active element of the other branch, so as to form a voltage amplifier. Each active element is controlled by means of a high impedance circuit element. A microswitch connects the two branches together is inserted between the two active elements.

Abstract: A process for determining a quiescent power supply current (I.sub.DDQ) of a device under test (DUT) at a first node. The process includes the steps of providing a reference current to the first node and decoupling a power supply from the first node. A first node voltage is determined at a first time after the power supply is decoupled from the first node. The first node voltage is determined at a second time after the first time. If the first node voltage increases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is less than the reference current. If the first node voltage decreases from the first time to the second time, it is indicated that the I.sub.DDQ of the DUT is greater than the reference current.

Abstract: This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned to accomplish multiple purposes. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure (for a memory wafer the word length, number of banks of words, and number of words per bank). The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing (testing uses conventional techniques) for good and bad elements.

Abstract: A row decoder circuit operates in a memory integrated circuit, such as a dynamic random access memory (DRAM), having an array of memory cells including row and columns. An address decode tree circuit receives address signals and provides decode signals being activated based on the state of the address signals. Row line driver circuits receive corresponding ones of the decode signals and an enable signal. Each row line driver circuit fires a corresponding row line when the enable signal is activated and the corresponding one of the decode signals is activated. Delay circuitry delays certain of the address signals to stagger the activation of certain of the decode signals to permit multiple row lines to fire in a single row address strobe (RAS) cycle.

Abstract: A pulse ramp control circuit allows for the program voltage applied to the control gate of a memory cell to be ramped from a low voltage to a high voltage in a precise manner. The ramp rate of this program voltage is primarily determined by a single capacitor and the bias current provided thereto. By providing a ramped program voltage to the memory array during programming operations, present embodiments effectively cover the entire distribution of program voltage v. program current for the memory cells to be programmed, thereby minimizing over-program and under-program conditions without reducing program time.

Abstract: A circuit for selectively programming a single bit in non-volatile memory is disclosed. The circuit consists of at least one comparator, at least one transistor, and at least one logic gate for each elementary memory in the memory word. In operation, the circuit allows for individual correction of mis-programmed cells within the memory by comparing the actual contents of the memory with the desired contents. If the actual contents does not match the desired contents, that individual cell is re-programmed.

Abstract: A static random access memory (SRAM) cell includes a bistable diode and a load device serially connectable between two voltage potentials (VDD, Ground) with a gate device (field effect transistor) connected between a bit line and a common terminal of the bistable diode and load device and a control terminal of the gate device connected to a word line. The bistable diode includes a GeSi structure between a p-doped semiconductor region and a spaced n-doped semiconductor region. The GeSi structure can be a GeSi/Si superlattice and a .delta.-doped tunnel junction, a Ge.sub.x Si.sub.1-x multiple well structure, or a .delta.-doped tunnel junction.

Abstract: A semiconductor memory cell comprising a capacitor for storing data thereon, and a first transistor being switched in response to a logic state of a word line. The first transistor writes data on a bit line into the capacitor, reads the data stored on the capacitor and transfers the read data to the bit line. The semiconductor memory cell further comprises a second transistor being switched in response to the logic state of the word line. The second transistor writes data on a bit line bar into the capacitor, reads the data stored on the capacitor and transfers the read data to the bit line bar. The semiconductor memory cell further comprises a transistor device for holding the data stored on the capacitor. According to the present invention, the semiconductor memory cell has a reduced number of devices as compared with a conventional one to enhance a chip integration degree.

Abstract: A non-volatile data storage unit having a data input and a volatile memory device for storing data. The volatile memory device is preferably a latch circuit made up of a pair of cross-coupled inverter circuits which store the data in complementary form. A non-volatile memory device, such as a pair of flash memory cells, is included which also store data in complementary form. Control circuitry is provided for controlling the operation of the data storage unit, including circuitry for transferring data from the data input to the volatile memory device and circuitry for programming the non-volatile memory device with data from the volatile memory device. The storage unit also preferably includes circuitry for transferring data stored in the non-volatile memory device to the volatile memory device, with such transfer typically taking place after an interruption of power to the storage unit.

Abstract: An embodiment of the present invention provides a method to reduce a regulated power source voltage spike during operation of a dynamic random access memory by the steps of: providing a voltage spike reducer enabling pulse via a pulse generator circuit responsive to a pulse generator input signal; translating the voltage level of an unregulated power source via a level translation stage during the presence of the voltage spike reducer enabling pulse; amplifying a translated voltage level; and providing a measure of current from the unregulated power supply to the regulated power supply via a current driver stage that is responsive to the amplified translated voltage level translation.

Abstract: A semiconductor memory device having an internal copy function. The memory device includes a memory cell array composed of a plurality of memory cells coupled to a plurality of bit lines, a plurality of column selectors coupled between the bit lines and an input/output data line for being turned on in response to a column select signal, a data amplifying circuit coupled to the input/output data line for amplifying the readout data, a data storage for receiving and latching the amplified data, and a write driver for outputting the latched data to the input/output data line.

Abstract: A circuit and method for concurrently addressing at least two rows of memory cells of a memory array of a memory device. By concurrently addressing at least two rows of memory cells during testing of the memory device during a burn-in period, the memory device can be tested in a reduced time period.

Abstract: A helper flip-flop device is coupled to a pair of I/O DIGIT lines in a DC bias current sensing based dynamic random access memory (DRAM) device for ensuring that one of the DIGIT lines returns to as low a voltage as possible following a memory access. A sense amplifier is coupled to the I/O lines to amplify the differential voltage appearing on the lines following access of a memory cell. The helper flip-flop, when activated at the same time the DC bias is removed, sinks current from the low line to ground, effectively reducing its voltage to near ground to allow faster release of the row access signal.