Abstract: Mechanisms for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an exemplary embodiment, a tensile or compressive film is applied to the devices on the integrated circuit chip but is removed from those devices whose operation is to be modified. Thereafter, a tensile or compressive strain layer is applied to the devices whose film was removed. An additional mask layer may then be used to effect a halo or well implant to relax the strain on the devices not being protected by the mask layer. In this way, the current of the non-protected devices is reduced back to its original target design point.

Abstract: A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer) Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using Cl, F plasma) the portions of the hard mask which have been already partially etched away.

Abstract: To improve the laser annealing process for polycrystallizing amorphous silicon to form silicon thin films having large crystal particle diameters at a high throughput, the present invention is directed to a process of crystallization by irradiation of a semiconductor thin film formed on a substrate with pulsed laser light. The process comprises having a means to shape laser light into a linear beam and a means to periodically and spatially modulate the intensity of pulsed laser in the direction of the long axis of the linear beam by passing through a phase-shifting stripy pattern perpendicular to the long axis, and collectively forming for each shot a polycrystalline film composed of crystals which have grown in a certain direction over the entire region irradiated with the linear beam.

Abstract: A gate conductor is provided for a transistor pair including an n-type field effect transistor (“NFET”) having an NFET active semiconductor region and a p-type field effect transistor (“PFET”) having a PFET active semiconductor region, where the NFET and PFET active semiconductor regions are separated by an isolation region. An NFET gate extends in a first direction over the NFET active semiconductor region. A PFET gate extends in the first direction over the PFET active semiconductor region. A diffusion barrier is sandwiched between the NFET gate and the PFET gate. A continuous layer extends continuously in the first direction over the NFET gate and the PFET gate. The continuous layer contacts top surfaces of the NFET gate and the PFET gate and the continuous layer includes at least one of a semiconductor, a metal or a conductive compound including a metal.

Abstract: An insulating film includes an oxide of a metal selected from Hf and Zr, the oxide being doped by at least one of Ba, Sr and Mg. And the insulating film satisfies the following formula (1): 0.06 at %?[Ba]+[Sr]+[Mg]?1.4 at %??(1) wherein [Ba] represents atomic % of Ba, [Sr] represents atomic % of Sr, and [Mg] represents atomic % of Mg.

Abstract: In a module for an optical device as a semiconductor device module of the present invention, a bonding wire that electrically connects a substrate on which a conductor wiring is formed and an image pickup element as a semiconductor element is covered with a cover, and a holder as a lid is placed over the cover.

Abstract: Provided is a multicolor organic light emitting apparatus having a plurality of organic light emitting devices formed on a substrate, for emitting two or more types of luminescent colors. A thickness of a layer formed between a light emitting layer and a reflection surface of a cathode is the same as that of each of first and second organic light emitting devices, and an optical distance between a light emitting surface of each of the light emitting layers and the reflection surface of the cathode is adjusted such that each thickness of the light emitting layers is varied to enhance light emitted from the light emitting layers by optical interference.

Abstract: A method for making an electronic device may include forming a poled superlattice comprising a plurality of stacked groups of layers and having a net electrical dipole moment. Each group of layers of the poled superlattice may include a plurality of stacked semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon. The at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include coupling at least one electrode to the poled superlattice.

Abstract: The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.

Abstract: A method of manufacturing an active matrix substrate includes forming wiring lines each having a matrix pattern on a substrate such that a wiring line extending in any one of a first direction and a second direction is separated from another wiring line at an intersection; forming a laminated portion composed of an insulating layer and a semiconductor layer on a portion of the wiring line and the intersection; and forming a conductive layer electrically connecting the separated wiring line, and a pixel electrode electrically connected to the wiring line via the semiconductor layer on the laminated portion.

Abstract: A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region.

Abstract: A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.

Abstract: A backside illuminated CMOS image sensor having an silicon layer with a front side and a backside, the silicon layer liberates charge when illuminated from the backside with light, an active pixel circuitry located on the front side of the semiconductor layer, a pinned photodiode adjacent to the active pixel circuitry on the front side of the semiconductor layer and configured to collect charge liberated in the semiconductor layer, and an implant located in the semiconductor layer, underneath the active pixel circuitry, for allowing charge liberated in the semiconductor layer to drift from the backside of the semiconductor layer to the pinned photodiode on the front side of the semiconductor layer.

Abstract: Electronic devices that include an acene-thiophene copolymer and methods of making such electronic devices are described. More specifically, the acene-thiophene copolymer has attached silylethynyl groups. The copolymer can be used, for example, in a semiconductor layer or in a layer positioned between a first electrode and a second electrode.

Abstract: In a dual damascene process to form a fine interconnection structure, a semiconductor manufacturing method includes: forming a first film to be etched on an insulating layer on a semiconductor substrate; forming a first mask film with an opening on the first film; forming a second film to be etched on the first mask film, burying the opening; forming a second mask film on the second film to be etched; forming an interconnection pattern in the second mask film in the upper portion of the opening; forming an interconnection pattern by etching the second film using the second mask film, forming a via pattern by etching the first film to be etched using the first mask film; and forming a via hole and an interconnection trench in the upper portion of the via hole in the insulating layer by selectively etching the insulating layer using the interconnection and via patterns.

Abstract: A fuse structure and a method for operating the same. The fuse structure operating method includes providing a structure. The structure includes (a) an electrically conductive layer and (b) N electrically conductive regions hanging over without touching the electrically conductive layer. N is a positive integer and N is greater than 1. The N electrically conductive regions are electrically connected together. The structure operating method further includes causing a first electrically conductive region of the N electrically conductive regions to touch the electrically conductive layer without causing the remaining N?1 electrically conductive regions to touch the electrically conductive layer.

Abstract: A method and a fused compound wafer including at least one first MEMS sensor and at least second MEMS sensor includes a first wafer. The first wafer includes at least one first MEMS sensor first subassembly and at least one second MEMS sensor first subassembly. A second wafer includes at least one first MEMS sensor second subassembly, at least one second MEMS sensor second assembly, and a fusing matrix. The fusing matrix includes a first joint configured to encapsulate each of the at least one first MEMS sensor first assembly and each of the at least one first MEMS sensor second assembly forming each at least one first MEMS sensor. A second joint is configured to encapsulate each of the at least one second MEMS first subassembly and each of the at least one second MEMS second subassembly forming each at least one second MEMS sensor.

Abstract: A power module fabrication method and structure thereof is disclosed.

Abstract: A one time programmable memory including a substrate, a plurality of isolation structures, a first transistor, and a second transistor is provided. The isolation structures are disposed in the substrate for defining an active area. A recess is formed on each of the isolation structures so that the top surface of the isolation structure is lower than that of the substrate. The first transistor is disposed on the active area of the substrate and is extended to the sidewall of the recess. The gate of the first transistor is a select gate. The second transistor is disposed on the active area of the substrate and is connected to the first transistor in series. The gate of the second transistor is a floating gate which is disposed across the substrate between the isolation structures in blocks and is extended to the sidewall of the recess.

Abstract: The present invention relates to a display device, such as an organic electroluminescent device, for preventing corrosion of a signal line. A display device according to the present invention, comprising a substrate; a first electrode layer disposed over the substrate; a second electrode layer disposed to cover the first electrode layer and configured to electrically communicate with the first electrode layer; and a pixel disposed over the substrate, wherein a signal line is defined as an electrode layer including the first electrode layer and the second electrode layer, wherein the first electrode layer is in electrical communication with the pixel. The display device according to the present invention can prevent the material of the signal line from being corroded. Also, the device can prevent the reduction of brightness and the increase of power consumption.