Patents Examined by Trung Dang
  • Patent number: 7847303
    Abstract: A warm white light emitting apparatus includes a first light emitting diode (LED)-phosphor combination to generate a base light that is white or yellowish white and a second LED-phosphor combination to generate a Color Rendering Index (CRI) adjusting light. The base light and the CRI adjusting light together make a warm white light having a color temperature of 2500 to 4500K.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: December 7, 2010
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Jung Hwa Jung, Sang Min Lee
  • Patent number: 7833885
    Abstract: Methods for forming a microcrystalline silicon layer in a thin film transistor structure are provided. In one embodiment, a method for forming a microcrystalline silicon layer includes providing a substrate in a processing chamber, supplying a gas mixture having a hydrogen-based gas, a silicon-based gas and an argon gas into the processing chamber, the gas mixture having a volumetric flow ratio of the hydrogen-based gas to the silicon-based gas greater than about 100:1, wherein a volumetric flow ratio of the argon gas to the total combined flow of hydrogen-based gas and the silicon-based gas is between about 5 percent and about 40 percent, and maintaining a process pressure of the gas mixture within the processing chamber at greater than about 3 Torr while depositing a microcrystalline silicon layer on the substrate.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: November 16, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Tae Kyung Won, Soo Young Choi, Dong Kil Yim, Jriyan Jerry Chen, Beom Soo Park
  • Patent number: 7829918
    Abstract: The invention discloses a FET based sensor. The FET based sensor according to an embodiment of the invention includes a substrate, an InN material layer, a source terminal and a drain terminal. The InN material layer is formed over the substrate and has an upper surface. The upper surface thereon provides an analyte sensing region. The InN material layer serves as a current channel between the source terminal and the drain terminal. Thereby, ions adsorbed by the analyte sensing region induce a variation of a current flowing through the current channel, and the variation is further interpreted as a characteristic of the analyte.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: November 9, 2010
    Inventors: Jer-Liang Andrew Yeh, Shangjr Gwo
  • Patent number: 7829897
    Abstract: An array substrate of a liquid crystal display device having a color filter on a gate metal layer, and a data metal layer formed on the color filter. First a gate insulating layer is formed on the gate metal layer to protect and a second gate insulating layer is formed on the color filter layer. Gate lines and gate electrodes are formed in direct contact with the substrate, and color filters are formed on the gate electrodes. To protect gate lines in the patterning process of color filters, a first gate insulating layer is formed on the gate lines and electrodes. Therefore, a high aperture ratio may be enhanced, and the manufacturing yield may be increased.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: November 9, 2010
    Assignee: Samsung Electronics Co, Ltd.
    Inventors: Jean-Ho Song, Chong-Chul Chai, Jin-Ho Ju, Joo-Ae Youn, Jun-Hyung Souk, Min Kang
  • Patent number: 7829964
    Abstract: A magnetic memory element utilizing spin transfer switching includes a pinned layer, a tunneling barrier layer and a free layer structure. The tunneling barrier layer is disposed on the pinned layer. The free layer structure includes a composite free layer. The composite free layer includes a first free layer, an insert layer and a second free layer. The first free layer is disposed on the tunneling barrier layer and has a first spin polarization factor and a first saturation magnetization. The insert layer is disposed on the first free layer. The second free layer is disposed on the insert layer and has a second spin polarization factor smaller than the first spin polarization factor and a second saturation magnetization smaller than the first saturation magnetization. Magnetization vectors of the first free layer and the second free layer are arranged as parallel-coupled.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: November 9, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Wei-Chuan Chen, Cheng-Tyng Yen, Ding-Yeong Wang
  • Patent number: 7825429
    Abstract: A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: November 2, 2010
    Assignee: Intersil Americas Inc.
    Inventor: James E. Vinson
  • Patent number: 7825408
    Abstract: A programmable semiconductor device has a switch element in an interconnection layer, wherein in at least one of the inside of a via, interconnecting a wire of a first interconnection layer and a wire of a second interconnection layer, a contact part of the via with the wire of the first interconnection layer and a contact part of the via with the wire of the second interconnection layer, there is provided a variable electrical conductivity member, such as a member of an electrolyte material. The via is used as a variable electrical conductivity type switch element or as a variable resistance device having a contact part with the wire of the first interconnection layer as a first terminal and having a contact part with the wire of the second interconnection layer as a second terminal.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: November 2, 2010
    Assignee: NEC Corporation
    Inventors: Shunichi Kaeriyama, Masayuki Mizuno
  • Patent number: 7825418
    Abstract: A light emitting diode (LED) includes a transparent substrate, a first type cladding layer, an active layer, a second type cladding layer, and first and second electrodes. The first type cladding layer is disposed on the transparent substrate. The active layer and the second electrode are juxtaposed on the first type cladding layer. The second type cladding layer is disposed on the active layer. The second electrode is disposed on the second type cladding layer. The first and second type cladding layers are doped with nanoparticles.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: November 2, 2010
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Ga-Lane Chen
  • Patent number: 7821017
    Abstract: The invention discloses a method for fabricating a light-emitting diode. In an embodiment of the invention, the method comprises the following steps of (a) preparing a substrate; (b) forming an epitaxial layer on the substrate, wherein the epitaxial layer has an upper surface; (c) forming a mask layer on a first region of the upper surface of the epitaxial layer; (d) forming a semiconductor multi-layer structure on a second region of the upper surface of the epitaxial layer, wherein the second region is distinct from the first region; (e) removing the mask layer formed on the first region of the upper surface of the epitaxial layer; and (f) forming an electrode on the first region of the upper surface of the epitaxial layer.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: October 26, 2010
    Assignee: HUGA Optotech Inc.
    Inventors: Chi-Shen Lee, Su-Hui Lin
  • Patent number: 7821082
    Abstract: A lateral diffused metal oxide semiconductor transistor is disclosed. A p-type bulk is disposed on a substrate. An n-type well region is disposed in the p-type bulk. A plurality of field oxide layers are disposed on the p-type bulk and the n-type well region. A gate structure is disposed on a portion of the p-type bulk and one of the plurality of field oxide layers. At least one deep trench isolation structure is disposed in the p-type bulk and adjacent to the n-type well region.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: October 26, 2010
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Kwang-Ming Lin, Shih-Chieh Pu, Shih-Chan Chen
  • Patent number: 7816670
    Abstract: An organic memory device and a method for fabricating the memory device are provided. The organic memory device may include a first electrode, a second electrode, and an ion transfer layer between the first electrode and the second electrode. The organic memory device may have lower operating voltage and current, and may be fabricated at lower costs.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: October 19, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won Jae Joo, Tae Lim Choi, Sang Kyun Lee
  • Patent number: 7811884
    Abstract: When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: October 12, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Ikuko Kawamata, Yasuyuki Arai
  • Patent number: 7812401
    Abstract: An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm?3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.
    Type: Grant
    Filed: January 18, 2010
    Date of Patent: October 12, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Borna Obradovic, Shashank Ekbote, Mark Visokay
  • Patent number: 7807499
    Abstract: A manufacturing method of a stacked module includes a step of fabricating the first wiring board which includes a wiring pattern provided on at least one of a surface and an inner portion and a bump electrode which is integrated from the simultaneous sintering with the wiring pattern, and which extends in the vertical direction, a step of layering the first wiring board with the second wiring board having the wiring pattern provided on at least one of the surface and the inner portion thereof to be connected to the second wiring board via the bump electrode.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: October 5, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yoshihiko Nishizawa
  • Patent number: 7808027
    Abstract: An MTJ MRAM cell and its method of formation are described. The cell includes a composite free layer having the general form (Ni88Fe12)1-xCo100x—Ni92Fe8 with x between 0.05 and 0.1 that provides low magnetization and negative magnetostriction. The magnetostriction can be tuned to a low value by a multilayer capping layer that includes a positive magnetostriction layer of NiFeHf(15%). When this cell forms an MRAM array, it contributes to a TMR?26%, a TMR/Rp—cov?15.5 and a high AQF (array quality factor) for write operations.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: October 5, 2010
    Assignee: MagIC Technologies, Inc.
    Inventors: Cheng T. Horng, Ru-Ying Tong
  • Patent number: 7804088
    Abstract: A semiconductor device includes a substrate and a semiconductor layer having a channel region, the channel region is made from an oxide semiconductor which satisfies Vc/Va>4 where Vc is a volume ratio of a crystalline component and Va is a volume ratio of a non-crystalline component.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: September 28, 2010
    Assignee: FUJIFILM Corporation
    Inventors: Atsushi Tanaka, Ken-ichi Umeda, Kohei Higashi, Maki Nangu
  • Patent number: 7804105
    Abstract: In a side view type light emitting diode (LED) package, a lead frame portion and lead frame electrical contact portions are exposed outside a package body to serve as an additional heat dissipation path. The side view type LED package includes an LED chip, a package body having a side surface with an opening for receiving the LED chip, and lead frames for applying a current to the LED chip. The lead frames include inner leads electrically connected to the LED chip within the package body; electrical contact lower legs extending from the inner leads to a lower portion of the package body and exposed outside the package body in the vicinity of a lower surface of the package body perpendicular to the side surface; and a heat dissipation means extending, separately from the electrical contact lower legs, from at least one of the inner leads outside the package body.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: September 28, 2010
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Nam Young Kim, Tae Kwang Kim, Kyoung Bo Han, Myung Hee Lee
  • Patent number: 7804099
    Abstract: A solid-state light source includes at least one stack of light emitting elements. The elements are an inorganic light emitting diode chip and at least one wavelength conversion chip or the elements are a plurality of light emitting diode chips and one or more optional wavelength conversion chips. The wavelength conversion chip may include an electrical interconnection means. The light emitting diode chip may include at least one GaN-based semiconductor layer that is at least ten microns thick and that is fabricated by hydride vapor phase epitaxy. A method is described for fabricating the solid-state light source.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: September 28, 2010
    Assignee: Goldeneye, Inc.
    Inventors: Karl W. Beeson, Scor M. Zimmerman, William R. Livesay
  • Patent number: 7804179
    Abstract: A method and product which provides a thin metal or ceramic plate to the top of a plastic grid array (PGA) as a stiffener to maintain its flatness over temperature during a column attach process, and the columns are used for attachment to circuit boards or other circuit devices. These may be constructed in this manner initially or may be retrofitted plastic ball grid arrays from which the solder balls are removed and, the stiffener is attached to the top, and the solder columns have been added to replace the solder balls. The stiffener is a bonded thin metal or ceramic plate attached to the top of the PGA to maintain its flatness over temperature during the column attach process. An aluminum plate bonded to the top of a PGA results in a significant reduction in warping during a temperature cycle. This allows attachment of solder columns to the PBGA. The high melt solder columns are attached to an area array pattern on the PBGA substrate. This array is typically either a solid or perimeter grid.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: September 28, 2010
    Assignee: Lockheed Martin Corporation
    Inventors: Charles H. Dando, III, Stephen G. Gonya, William E. Murphy
  • Patent number: 7795629
    Abstract: A method for manufacturing a light-emitting diode display is provided. The method includes pre-fixing first, second, and third light-emitting diodes on a light emitting unit production substrate to produce light-emitting units each including first, second, and third light-emitting diodes, first electrodes of the first, second, and third light-emitting diodes being connected to a sub-common electrode. The method also includes transferring and fixing the light-emitting units from the light-emitting unit production substrate to a display substrate to produce a light-emitting diode display including the light-emitting units which are arranged in a first direction and a second direction perpendicular to the first direction (i.e., arranged in a two-dimensional matrix).
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: September 14, 2010
    Assignee: Sony Corporation
    Inventors: Toshihiko Watanabe, Masato Doi, Shoichi Muraguchi