Patents Examined by Trung Dang
  • Patent number: 7791091
    Abstract: A semiconductor light-emitting device (1) includes a semiconductor multilayer film (11), a base material (12) for supporting the semiconductor multilayer film (11), a first feed terminal (17a), and a second feed terminal (17b). A protruding portion (12c) is formed on the back surface (12b) of the base material (12) that is opposite to the principal surface (12a) facing the semiconductor multilayer film (11). The first and second feed terminals (17a, 17b) are formed in contact with at least one selected from the portions (12d) of the back surface (12b) other than the protruding portion (12c) and the sides (12e) of the base material (12). The end face (121c) of the protruding portion (12c) is insulated electrically from the first and second feed terminals (17a, 17b). With this configuration, the semiconductor light-emitting device can improve the heat dissipation and achieve high integration easily.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: September 7, 2010
    Assignee: Panasonic Corporation
    Inventor: Hideo Nagai
  • Patent number: 7786597
    Abstract: A multilayer wiring board includes: a substrate; connection pads arranged in a square grid fashion; and wiring patterns. Relationship between the connection pads and the wiring patterns satisfies: {(Ndl+1)P?d?s}/(w+s)>2Ndr+Ndl(a+1)+2a, wherein P is a pitch of the connection pads, d is a diameter of the connection pads, s is a minimum interval between the wiring patterns and is a minimum interval between the wiring pattern and the connection pad that are adjacent to each other, w is a minimum width of the wiring patterns, Ndl is the number of non-pad rows in each of the non-pad regions, Ndr is the number of non-pad columns in each of non-pad region, and a is an integer of (P?d?s)/(w+s).
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: August 31, 2010
    Assignee: Shinko Electric Industries Co., Ltd
    Inventors: Michio Horiuchi, Yasue Tokutake, Shigeaki Suganuma, Naoyuki Koizumi, Fumimasa Katagiri
  • Patent number: 7781847
    Abstract: A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths and exposing sidewalls of the dummy elements and portions of the top surface of the cap layer aside from the dummy elements. Deposit a spacer layer over the device covering the patterned dummy elements and exposed surfaces of the cap layer. Etch back the spacer layer forming sidewall spacers aside from the sidewalls of the patterned dummy elements spaced above a minimum spacing and forming super-wide spacers between sidewalls of the patterned dummy elements spaced less than the minimum spacing. Strip the patterned dummy elements. Expose portions of the substrate aside from the sidewall spacers. Pattern exposed portions of the substrate by etching into the substrate.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: August 24, 2010
    Assignee: International Business Machines Corporation
    Inventor: Haining S. Yang
  • Patent number: 7781794
    Abstract: The present invention provides a resin sheet for encapsulating an optical semiconductor element, the resin sheet containing an encapsulation resin layer, an adhesive resin layer, a metal layer and a protective resin layer, in which the encapsulation resin layer and the metal layer adhered onto the adhesive resin layer are disposed adjacently to each other, the protective resin layer is laminated on the encapsulation resin layer and the metal layer so as to cover both the encapsulation resin layer and the metal layer, and the encapsulation resin layer has a taper shape expanding toward the protective resin layer; and an optical semiconductor device containing an optical semiconductor element encapsulated by using the resin sheet. The optical semiconductor element encapsulation resin sheet of the invention can be suitably used for back lights of liquid crystal screens, traffic signals, large-sized outdoor displays, billboards and the like.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: August 24, 2010
    Assignee: Nitto Denko Corporation
    Inventors: Ichiro Suehiro, Kouji Akazawa, Hideyuki Usui
  • Patent number: 7772691
    Abstract: A method of forming a package structure includes providing a plurality of dies; attaching the plurality of dies onto a heat-dissipating plate; and sawing the heat-dissipating plate into a plurality of packages, each including one of the plurality of dies and a piece of the heat-dissipating plate.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: August 10, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Hui Lee, Mirng-Ji Lii, Chien-Hsiun Lee
  • Patent number: 7772662
    Abstract: The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH3 or H2 as pretreatment. Thereafter, a tensile stress silicon nitride film to impose tensile stress on an MTJ device is formed over a clad layer and over an interlayer dielectric film where the clad layer is not formed. Successively, a compressive stress silicon nitride film to impose compressive stress on the MTJ device is formed over the tensile stress silicon nitride film. The conditions for forming the tensile stress silicon nitride film and the compressive stress silicon nitride film are as follows: a parallel plate type plasma CVD apparatus is used; the RF power is set in the range of 0.03 to 0.4 W/cm2; and the film forming temperature is set in the range of 200° C. to 350° C.
    Type: Grant
    Filed: April 16, 2009
    Date of Patent: August 10, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsunori Murata, Mikio Tsujiuchi
  • Patent number: 7768093
    Abstract: A semiconductor device has a heavily doped substrate and an upper layer with doped silicon of a first conductivity type disposed on the substrate, the upper layer having an upper surface and including an active region that comprises a well region of a second, opposite conductivity type. An edge termination zone has a junction termination extension (JTE) region of the second conductivity type, the region having portions extending away from the well region and a number of field limiting rings of the second conductivity type disposed at the upper surface in the junction termination extension region.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: August 3, 2010
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Frank Hille, Thomas Raker
  • Patent number: 7768104
    Abstract: An apparatus and method for a two semiconductor device package where the semiconductor devices are connected in electrical series. The first device is mounted P-side down on an electrically conductive substrate. Non-active area on the P side is isolated from the electrically conductive substrate. The second device is mounted P-side up at a spaced apart location on the substrate. Opposite sides of each are electrically connected to leads to complete the series connection of the two devices. A method of manufacturing such a package includes providing an electrically conductive lead frame, mounting one device P-side up and flipping the other device and mounting it P-side down on the lead frame with non-active area of the P side isolated from the lead frame, and connecting the other side of each device to separate leads. Isolation of the non-active area of the P side of the device can be through modification of the substrate or lead frame surface by grooves or raised portions.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: August 3, 2010
    Assignee: Vishay General Semiconductor, Inc.
    Inventors: Ta-Te Chou, Hui-Ying Ding, Yun Zhang, Hong-Yun He, Li-Zhu Hao
  • Patent number: 7763895
    Abstract: A flexible light source device including a substrate, a light emitting device, a molding compound, a dielectric layer, and a metal line is provided. The substrate has a first surface, a second surface opposite to the first surface, and a first opening. The light emitting device is disposed on the first surface of the substrate and covers the first opening. The molding compound is located above the first surface and covers the light emitting device. The dielectric layer is disposed on the second surface and covers a sidewall of the first opening. The dielectric layer has a second opening which exposes part of the light emitting device. The metal line is disposed on the dielectric layer, wherein the metal line is electrically connected to the light emitting device via the second opening in the dielectric layer. Additionally, a fabrication method of the flexible light source device is also provided.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: July 27, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Zhi-Cheng Hsiao, Chao-Kai Hsu, Yu-Hua Chen
  • Patent number: 7763960
    Abstract: A semiconductor device of the present invention includes: a plurality of semiconductor chips each having a chip size package structure; and a substrate bonded via an adhesive material to an opposite surface in each of the plurality of semiconductor chips that is opposite to a connection surface that is provided with solder balls (external connection terminals). Thereby, the plurality of semiconductor chips are connected to each other.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: July 27, 2010
    Assignee: Panasonic Corporation
    Inventors: Tatsuya Morishita, Osamu Ishikawa
  • Patent number: 7763984
    Abstract: A semiconductor package and a method for manufacturing the same. The semiconductor package includes a substrate having connection pads formed on one surface thereof, a semiconductor chip having bonding pads formed on one surface thereof to correspond to the connection pads; bumps for electrically connecting the connection pads and the bonding pads with each other, a coating layer located on exposed surface portions of the bonding pads and the connection pads to prevent voids from being formed in spaces between the substrate and the semiconductor chip, and an underfill member filled in the spaces over the coating layer.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: July 27, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jong Hoon Kim, Joon Won Kim
  • Patent number: 7759767
    Abstract: An electrical fuse has a region of a first conductivity type in a continuous type polysilicon of a second conductivity type that is opposite the first conductivity type. In one embodiment of the invention the PN junction between the region and the poly fuse is reverse biased.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: July 20, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Paul R. Fournier, Susan Stock
  • Patent number: 7750359
    Abstract: A broad bandwidth light source including: a solid state light emitting device that generates short wavelength light; and quantum dot material and phosphor material that are each irradiated by some of the short wavelength light. The short wavelength light has a spectrum with a first peak wavelength shorter than about 500 nm. The quantum dot material absorbs some of the short wavelength light and reemits it as long wavelength light having a spectrum with a second peak wavelength longer than about 600 nm. The phosphor material absorbs some of the short wavelength light and reemits it as mid wavelength light having a spectrum with a peak wavelength between the first and second peak wavelength. The light source is configured such that some of each light (short, mid, and long wavelength) is emitted coincidentally as a light having a chromaticity value near the blackbody locus and a color rendering index greater than 80.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: July 6, 2010
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Nadarajah Narendran, Yimin Gu
  • Patent number: 7741725
    Abstract: With a semiconductor apparatus package of example embodiments of the technology disclosed herein and a method of producing the semiconductor apparatus package, the semiconductor apparatus package includes a circuit board and a semiconductor device sealed with sealing resin. The circuit board has a groove in a section of a surface of the circuit board. The section is outside of the resin sealing section, and the surface includes the resin sealing section. The groove is at least partially filled with sealing resin having seeped from a resin sealing section. Thus, in the semiconductor apparatus package including the circuit board, which is exposed from the resin sealing section, and the semiconductor device sealed on the circuit board with the sealing resin, the spread of a thin resin film onto that exposed circuit board resulting from seepage of resin sealing the semiconductor device is prevented.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: June 22, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazuo Tamaki
  • Patent number: 7736969
    Abstract: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: June 15, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Todd R. Abbott, Homer M. Manning
  • Patent number: 7732810
    Abstract: An electronic device having a substrate structure having an undercut region is provided and further included is a method for forming an undercut region of a substrate structure. The method includes forming a patterned protective layer over a first electrode. The method also includes forming the substrate structure over the patterned protective layer. An opening within the substrate structure overlies an exposed portion of the substrate structure. The method further includes removing the exposed portion of the patterned protective layer, thereby exposing a portion of the first electrode and forming an undercut region of the substrate structure. The method still further includes depositing a liquid over the first electrode after removing the exposed portion of the patterned protective layer, and solidifying the liquid to form a solid layer.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: June 8, 2010
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: Nugent Truong, Charles Douglas Macpherson
  • Patent number: 7732353
    Abstract: Methods for forming a denuded zone in an oxygen-containing semiconductor wafer using rapid laser annealing (RLA) are disclosed. The method includes scanning an intense beam of laser radiation over the surface of the wafer to raise the temperature of each point on the wafer surface to be at or near the wafer's melting temperature for a time period on the order of a millisecond or so. This rapid heating and cooling causes oxygen in the wafer near the wafer surface to diffuse out from the wafer surface. Oxygen in the body of the wafer remains unheated and thus does not diffuse toward the wafer surface. The result is an oxygen-depleted zone—called a “denuded zone”—formed immediately adjacent the wafer surface. The methods further include forming a semiconductor device feature in the denuded zone such as by implanting the wafer with dopants.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: June 8, 2010
    Assignee: Ultratech, Inc.
    Inventor: Israel Beinglass
  • Patent number: 7728445
    Abstract: A semiconductor device production method which includes steps of: preparing a wafer on which multiple integrated circuits are formed on a principal face; forming a rewiring which is electrically connected to the integrated circuits via a pad electrode; and dicing the wafer after forming an electrode terminal on the rewiring, including steps of: forming a first resin layer by sealing at least the rewiring and the electrode terminal formed on the principal face of the wafer with a first resin; processing a first dicing from a back face of the wafer to the principal face of the wafer or halfway to the first resin layer when the first resin layer is formed; forming a second resin layer by sealing a cut line outlined upon the first dicing and the back face of the wafer continuously with a first resin; and processing a second dicing while leaving the second resin layer which covers a side face outlined upon the first dicing.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: June 1, 2010
    Assignee: Yamaha Corporation
    Inventors: Taketoshi Nakamura, Hiroshi Saitoh
  • Patent number: 7728336
    Abstract: In an SiC vertical MOSFET comprising a channel region and an n-type inverted electron guide path formed through ion implantation in a low-concentration p-type deposition film, the width of the channel region may be partly narrowed owing to implantation mask positioning failure, and the withstand voltage of the device may lower, and therefore, the device could hardly satisfy both low on-resistance and high withstand voltage. In the invention, second inverted layers (41, 42) are provided at the same distance on the right and left sides from the inverted layer (40) to be the electron guide path in the device, and the inverted layers are formed through simultaneous ion implantation using the same mask, and accordingly, the length of all the channel regions in the device is made uniform, thereby solving the problem.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: June 1, 2010
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Tsutomu Yatsuo, Shinsuke Harada, Mitsuo Okamoto, Kenji Fukuda, Makoto Kato
  • Patent number: 7723775
    Abstract: A NAND flash memory device includes a plurality of active regions extending in a first direction on a substrate, the active regions including a first well of a first conductivity, a plurality of word lines extending on the first well in a second direction perpendicular to the first direction, first and second dummy word lines extending in a second direction on the first well, the first and second dummy word lines being separated from each other to define an intermediate region therebetween, the first and second dummy word lines being adapted to receive a substantially constant bias voltage of about 0 V, and at least one contact in an active region in the intermediate region between the first and second dummy word lines.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: May 25, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-jun Hwang, Jae-kwan Park, Jee-hoon Han, So-wi Jin, Nam-su Lim