Patents Examined by Trung Dang
  • Patent number: 7675098
    Abstract: A complementary metal oxide semiconductor (CMOS) image sensor including a semiconductor substrate having an inclined groove with an inclined surface and a light reception surface perpendicular to the semiconductor substrate, and a device forming area adjacent the light reception surface. A reflection film selectively formed on and/or over the inclined surface, a plurality of photodiodes substantially perpendicular to the surface of the substrate; and at least one MOS transistor formed on the surface of the device forming area.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: March 9, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jeong Su Park
  • Patent number: 7670919
    Abstract: An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: John J. Tang, Xiang Yin Zeng, Jiangqi He, Ding Hai
  • Patent number: 7670870
    Abstract: A method of manufacturing an organic thin film transistor characterized by low costs and high performances, the method in which the self-assemble monolayer is formed in a short period of time, and the organic thin film transistor are provided. A method of manufacturing an organic thin film a transistor having a gate electrode, a semiconductor layer, a source electrode, and a drain electrode on a substrate, wherein a semiconductor solution as a mixture of the self-assembled monolayer material and organic semiconductor material is coated between the source electrode and drain electrode, whereby a semiconductor layer is formed.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: March 2, 2010
    Assignee: Konica Minolta Holdings, Inc.
    Inventors: Tomoo Izumi, Masakazu Okada
  • Patent number: 7671360
    Abstract: A phase change memory includes a sidewall insulation film and a heater electrode which are formed in a contact hole formed in an interlayer insulation film on a lower electrode. The heater electrode has a recessed structure. In a recessed area surrounded by the sidewall insulation film, the heater electrode and a phase change film are contacted with each other. A phase change region is formed only in an area contacted with the sidewall insulation film. The sidewall insulation film is an anti-oxidizing insulation film. The phase change region and the heater electrode which are heated to a high temperature upon rewriting are not contacted with the interlayer insulation film as an oxidizing insulation film.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: March 2, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Natsuki Sato, Tsutomu Hayakawa
  • Patent number: 7671462
    Abstract: A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region.
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: March 2, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Kozo Sakamoto, Toshiaki Ishii
  • Patent number: 7667285
    Abstract: A protective photochromic barrier film for a light-sensitive printed electronic substrate. Light-sensitive semiconductor devices on a dielectric substrate are electrically connected by conductors. A barrier layer containing photochromic dyes covers some or all of the light-sensitive semiconductor devices. Upon exposure to visible, infrared, or ultraviolet light, the photochromic dyes change chemical structure and decrease the amount of visible or non-visible light that can impinge upon the light-sensitive electronic devices. Upon removal of the visible or non-visible light, the photochromic dyes either revert to their original structure or maintain their altered state.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: February 23, 2010
    Assignee: Motorola, Inc.
    Inventors: Jerzy Wielgus, Daniel R. Gamota, John B. Szczech, Jie Zhang
  • Patent number: 7666757
    Abstract: An object is to provide a method for manufacturing an SOI substrate, by which defective bonding can be prevented. An embrittled layer is formed in a region of a semiconductor substrate at a predetermined depth; an insulating layer is formed over the semiconductor substrate; the outer edge of the semiconductor substrate is selectively etched on the insulating layer side to a region at a greater depth than the embrittled layer; and the semiconductor substrate and a substrate having an insulating surface are superposed on each other and bonded to each other with the insulating layer interposed therebetween. The semiconductor substrate is heated to be separated at the embrittled layer while a semiconductor layer is left remaining over the substrate having an insulating surface.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: February 23, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideto Ohnuma
  • Patent number: 7663190
    Abstract: A tunable voltage isolation ground to ground ESD clamp is provided. The clamp includes a dual-direction silicon controlled rectifier (SCR) and trigger elements. The SCR is coupled between first and second grounds. The trigger elements are also coupled between the first and second grounds. Moreover, the trigger elements are configured to provide a trigger current to the dual-direction silicon controlled rectifier when a desired voltage between the first and second grounds is reached.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: February 16, 2010
    Assignee: Intersil Americas Inc.
    Inventor: James E. Vinson
  • Patent number: 7663237
    Abstract: A semiconductor structure and a method of forming the same using replacement gate processes are provided. The semiconductor structure includes a butted contact coupling a source/drain region, or a silicide on the source/drain region, of a first transistor and a gate extension. The semiconductor structure further includes a contact pad over the source/drain region of the first transistor and electrically coupled to the source/drain region. The addition of the contact pad reduces the contact resistance and the possibility that an open circuit is formed between the butted contact and the source/drain region. The contact pad preferably has a top surface substantially leveled with a top surface of the gate extension.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: February 16, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Ching Peng, Chloe Hsin-yi Chen, David Hsu-Wei Lwu, Shyue-Shyh Lin, Wei-Ming Chen
  • Patent number: 7659134
    Abstract: Microelectronic imagers and methods of manufacturing such microelectronic imagers are disclosed. In one embodiment, a method for manufacturing a microelectronic imager can include irradiating selected portions of an imager housing unit. The housing unit includes a body having lead-in surfaces and a support surface that define a recess sized to receive a microelectronic die. The method also includes depositing a conductive material onto the irradiated portions of the housing unit and forming electrically conductive traces. The method further includes coupling a plurality of terminals at a front side of a microelectronic die to corresponding electrically conductive traces in the recess in a flip-chip configuration. The microelectronic die includes an image sensor aligned with at least a portion of an optical element carried by the housing unit and at least partially aligned with the recess.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: February 9, 2010
    Assignee: Aptina Imaging Corporation
    Inventors: Yong Poo Chia, Yong Loo Neo, Meow Koon Eng
  • Patent number: 7659171
    Abstract: A method for forming a borderless contact for a semiconductor FET (Field Effect Transistor) device, the method comprising, forming a gate conductor stack on a substrate, forming spacers on the substrate, such that the spacers and the gate conductor stack partially define a volume above the gate conductor stack, wherein the spacers are sized to define the volume such that a stress liner layer deposited on the gate conductor stack substantially fills the volume, depositing a liner layer on the substrate, the spacers, and the gate conductor stack, depositing a dielectric layer on the liner layer, etching to form a contact hole in the dielectric layer, etching to form the contact hole in the liner layer, such that a portion of a source/drain diffusion area formed in the substrate is exposed and depositing contact metal in the contact hole.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: February 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Steven J Holmes, David V Horak, Charles W. Koburger, III
  • Patent number: 7652322
    Abstract: In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: January 26, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-yong Choi, Chang-woo Oh, Dong-gun Park, Dong-won Kim, Yong-kyu Lee
  • Patent number: 7649257
    Abstract: An integrated circuit and methods of forming and using the integrated circuit. The circuit includes: a radiation-emitting layer over a selected region of a top surface of an integrated circuit chip, the radiation emitting layer comprising a first polymer or resin and a first radioactive material, the region smaller than a whole of the top surface of the integrated circuit chip, the region including a circuit that is liable to temporary failure when struck by radiation generated by the first radioactive material.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: January 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Gordon, Nancy C. LaBianca, Kenneth P. Rodbell
  • Patent number: 7645681
    Abstract: Conventional heat bonding and anodic bonding require heating at high temperature and for a long time, leading to poor production efficiency and occurrence of a warp due to a difference in thermal expansion, resulting in a defective device. Such a problem is solved. An upper wafer 7 made of glass and a lower wafer 8 made of Si are surface-activated using an energy wave before performing anodic bonding, thereby performing bonding at low temperature and increasing a bonding strength. In addition, preliminary bonding due to surface activation is performed before main bonding due to anodic bonding is performed in a separate step or device, thereby increasing production efficiency, and enabling bonding of a three-layer structure without occurrence of a warp.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: January 12, 2010
    Assignee: Bondtech, Inc.
    Inventor: Masuaki Okada
  • Patent number: 7646081
    Abstract: Method for forming a low dielectric constant structure on a semiconductor substrate by CVD processing. The method comprises using a precursor containing chemical compound having the formula of (R1-R2)n-Si—(X1)4-n, wherein X1 is hydrogen, halogen, acyloxy, alkoxy or OH group, R2 is an optional group and comprises an aromatic group having 6 carbon atoms and R1 is a substituent at position 4 of R2 selected from an alkyl group having from 1 to 4 carbon atoms, an alkenyl group having from 2 to 5 carbon atoms, an alkynyl group having from 2 to 5 carbon atoms, Cl or F; n is an integer 1-3. The present precursors allow for a lowering of the electronic dielectric constant compared to conventional dielectric materials, such as silicon dioxide or phenyl modified organo-containing silicon dioxide.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: January 12, 2010
    Assignee: Silecs Oy
    Inventor: Juha T. Rantala
  • Patent number: 7642203
    Abstract: Embodiments relate to a passivation layer for a semiconductor device that may be formed in a substrate having a plurality of semiconductor devices. The passivation layer may includes a first passivation layer, a second passivation layer, and a third passivation layer, and the passivation layer may have a laminated triple layer structure.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: January 5, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Seung Hyun Kim
  • Patent number: 7635630
    Abstract: A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and a trench diffusion area is formed under each trench. A vertical, non-volatile memory cell is formed on each sidewall of the trench. Each memory cell is comprised of a fixed threshold element located vertically between a pair of non-volatile gate insulator stacks. In one embodiment, each gate insulator stack is comprised of a tunnel insulator formed over the sidewall, a deep trapping layer, and a charge blocking layer. In another embodiment, an injector silicon rich nitride layer is formed between the deep trapping layer and the charge blocking layer.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: December 22, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 7633079
    Abstract: A programmable phase change material (PCM) structure includes a heater element formed at a BEOL level of a semiconductor device, the BEOL level including a low-K dielectric material therein; a first via in electrical contact with a first end of the heater element and a second via in electrical contact with a second end of the heater element, thereby defining a programming current path which passes through the first via, the heater element, and the second via; a PCM element disposed above the heater element, the PCM element configured to be programmed between a lower resistance crystalline state and a higher resistance amorphous state through the use of programming currents through the heater element; and a third via in electrical contact with the PCM element, thereby defining a sense current path which passes through the third via, the PCM element, the heater element, and the second via.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: December 15, 2009
    Assignee: International Business Machines Corporation
    Inventors: Kuang-Neng Chen, Bruce G. Elmegreen, Deok-Kee Kim, Chandrasekharan Kothandaraman, Lia Krusin-Elbaum, Chung H. Lam, Dennis M. Newns, Byeongju Park, Sampath Purushothaman
  • Patent number: 7633123
    Abstract: A semiconductor device includes: two main electrodes; multiple first regions; and multiple second regions. The first region having a first impurity concentration and a first width and the second region having a second impurity concentration and a second width are alternately repeated. A product of the first impurity concentration and the first width is equal to a product of the second impurity concentration and the second width. The first width is equal to or smaller than 4.5 ?m. The first impurity concentration is lower than a predetermined concentration satisfying a RESURF condition. A ratio between on-state resistances of the device at 27° C. and at 150° C. is smaller than 1.8.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: December 15, 2009
    Assignee: Denso Corporation
    Inventors: Shoichi Yamauchi, Hitoshi Yamaguchi, Yoshiyuki Hattori, Kyoko Okada
  • Patent number: 7633125
    Abstract: Integration of silicon boron nitride in high voltage semiconductors is generally described. In one example, a microelectronic apparatus includes a semiconductor substrate upon which transistors of an integrated circuit are formed, a plurality of transistor gates formed upon the semiconductor substrate, a gate spacer dielectric disposed between the gates, and a contact etch stop dielectric disposed upon the gates and gate spacer dielectric, the contact etch stop dielectric comprising silicon boron nitride (SiBN) to reduce breakdown of the contact etch stop dielectric in high voltage applications.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: December 15, 2009
    Assignee: Intel Corporation
    Inventors: Donghui Lu, Jun-Yen J. Tewg