Patents Examined by Tsz Chiu
  • Patent number: 10249802
    Abstract: A light emitting device includes a light emitting element having a first face, a second face opposing the first face, a plurality of side faces extending between the first face and the second face, a plurality of corners where the second face meets two of the plurality of side faces, and a pair of electrodes on a second face side of the light emitting element; a light transmissive member covering a portion of at least one of the side faces and a portion of an edge where said at least one side face meets the second face such that at least one of the plurality of corners is exposed from the light transmissive member; and a covering member covering the at least one exposed corner of the light emitting element and the exterior of the light transmissive member such that the pair of electrodes are exposed from the covering member.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: April 2, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Ikuko Baike, Ryo Suzuki
  • Patent number: 10242972
    Abstract: A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a circuit sub-layer formed in the dielectric layer; an electronic element disposed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; a plurality of conductive posts formed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; and an encapsulant formed on the first surface of the dielectric layer and encapsulating the electronic element and the conductive posts. Upper surfaces of the conductive posts are exposed from the encapsulant so as to allow another electronic element to be disposed on the conductive posts and electrically connected to the circuit sub-layer through the conductive posts, thereby overcoming the conventional drawback that another electronic element can only be disposed on a lower side of a package structure and improving the functionality of the package structure.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: March 26, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chang-Lun Lu, Shih-Ching Chen, Guang-Hwa Ma, Cheng-Hsu Hsiao
  • Patent number: 10217738
    Abstract: A semiconductor device includes a semiconductor substrate, a base region formed in the semiconductor substrate on a front surface side thereof, a gate trench extending from a front surface side of the base region and penetrating thorough the base region, and a dummy trench extending from the front surface side of the base region and penetrating thorough the base region, where a portion of the dummy trench that extends beyond a back surface of the base region is longer than a portion of the gate trench that extends beyond the back surface of the base region.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 26, 2019
    Assignee: SMK Corporation
    Inventor: Tatsuya Naito
  • Patent number: 10211380
    Abstract: Light emitting devices and components having excellent chemical resistance and related methods are disclosed. In one embodiment, a component of a light emitting device can include a silver (Ag) portion, which can be silver on a substrate, and a protective layer disposed over the Ag portion. The protective layer can at least partially include an inorganic material for increasing the chemical resistance of the Ag portion.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: February 19, 2019
    Assignee: Cree, Inc.
    Inventors: Shaow Lin, James Sievert, Jesse Colin Reiherzer, Barry Rayfield, Christopher P. Hussell
  • Patent number: 10204958
    Abstract: An infrared detector includes a substrate, a light blocking layer on the substrate, a lower electrode on the light blocking layer, the lower electrode electrically connected to the light blocking layer, a lower insulating layer on the light blocking layer, a first semiconductor layer on the lower insulating layer, a first source electrode and a first drain electrode on the first semiconductor layer, an upper insulating layer on the first semiconductor layer, and a first gate electrode on the upper insulating layer, the first gate electrode electrically connected to the lower electrode, where the first semiconductor layer includes a zinc and a nitrogen, and the first semiconductor layer is configured to generate electric charges by reacting with an infrared ray.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 12, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seong-Min Wang, Byeong-Hoon Cho
  • Patent number: 10179730
    Abstract: Disclosed examples include sensor apparatus and integrated circuits having a package structure with an internal cavity and an opening that connects of the cavity with an ambient condition of an exterior of the package structure, and an electronic sensor structure mechanically supported by wires in the cavity and including a sensing surface exposed to the cavity to sense the ambient condition of an exterior of the package structure.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: January 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Barry Jon Male, Benjamin Cook, Robert Alan Neidorff, Steve Kummerl
  • Patent number: 10170727
    Abstract: An organic electroluminescent device with a touch sensor including: a first substrate; a second substrate arranged opposite to the first substrate; an organic EL element layer arranged above the first substrate; a first sealing film arranged toward the second substrate of the organic EL element layer, covering the organic EL element layer, and including a first inorganic layer; plural first detection electrodes extending in one direction, and arranged in parallel toward the second substrate of the first sealing film; a second sealing film arranged toward the second substrate of the first detection electrodes, and including a second inorganic layer; plural second detection electrodes extending in another direction different from the one direction, and arranged in parallel toward the second substrate of the second sealing film; and a touch sensor control unit controlling a potential to detect a touch with a display surface.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: January 1, 2019
    Assignee: Japan Display Inc.
    Inventors: Toshihiro Sato, Ryoichi Ito
  • Patent number: 10163921
    Abstract: To improve reliability of a semiconductor device, a control transistor and a memory transistor formed in a memory cell region are configured to have a double-gate structure, and a transistor formed in a peripheral circuit region is configured to have a triple-gate structure. For example, in the memory transistor, a gate insulating film formed by an ONO film is provided between a memory gate electrode and sidewalls of a fin, and an insulating film (a stacked film of a multilayer film of an insulating film/an oxide film and the ONO film) thicker than the ONO film is provided between the memory gate electrode and a top surface of the fin. This configuration can reduce concentration of an electric field onto a tip of the fin, so that deterioration of reliability of the ONO film can be prevented.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: December 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuyoshi Mihara
  • Patent number: 10153219
    Abstract: A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-jun Jeon, Nae-in Lee, Byung-Iyul Park
  • Patent number: 10153382
    Abstract: A mechanical memory transistor includes a substrate having formed thereon a source region and a drain region. An oxide is formed upon a portion of the source region and upon a portion of the drain region. A pull up electrode is positioned above the substrate such that a gap is formed between the pull up electrode and the substrate. A movable gate has a first position and a second position. The movable gate is located in the gap between the pull up electrode and the substrate. The movable gate is in contact with the pull up electrode when the movable gate is in a first position and is in contact with the oxide to form a gate region when the movable gate is in the second position. The movable gate, in conjunction with the source region and the drain region and when the movable gate is in the second position, form a transistor that can be utilized as a non-volatile memory element.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: December 11, 2018
    Assignee: Massachusetts Institute of Technology
    Inventor: Carl O. Bozler
  • Patent number: 10147735
    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: December 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tadashi Iguchi, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
  • Patent number: 10141407
    Abstract: According to example embodiments, a graphene device includes a first electrode, a first insulation layer on the first electrode, an information storage layer on the first insulation layer, a second insulation layer on the information storage layer, a graphene layer on the second insulation layer, a third insulation layer on a first region of the graphene layer, a second electrode on the third insulation layer, and a third electrode on a second region of the graphene layer.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: November 27, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: David Seo, Ho-jung Kim, In-kyeong Yoo, Myoung-jae Lee, Seong-ho Cho
  • Patent number: 10121905
    Abstract: Provided is a semiconductor device including a transistor in which a first gate and a second gate are provided with a channel formation region provided therebetween and which achieves both control of the threshold voltage and an increase in the on-state current. In a period during which first voltage with which the transistor is turned off is supplied to the first gate, control voltage for controlling the threshold voltage is supplied to the second gate. In a period during which second voltage with which the transistor is turned on is supplied to the first gate, the second voltage is supplied to the first gate and voltage in which voltage based on change in the voltage of a signal supplied to the first gate is added to the control voltage is supplied to the second gate.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: November 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroyuki Miyake
  • Patent number: 10109701
    Abstract: An organic EL display device includes: a lower electrode; an upper electrode; a first organic layer which is disposed between the lower electrode and the upper electrode and is formed of a plurality of layers including a light emitting layer formed of an organic material that emits light; a metal wire that extends between the pixels within the display region; and a second organic layer which is formed of a plurality of layers the same as that of the first organic layer and which comes into contact with a part of the metal wire and does not come into contact with the first organic layer. The upper electrode comes into contact with the metal wire in the periphery of the second organic layer. Accordingly, it is possible to uniformize the potential of the upper electrode without reducing the light emission area.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: October 23, 2018
    Assignee: Japan Display Inc.
    Inventors: Yuko Matsumoto, Toshihiro Sato
  • Patent number: 10084032
    Abstract: A method of manufacturing a semiconductor device and the semiconductor device are provided in which a plurality of layers with cobalt-zirconium-tantalum are formed over a semiconductor substrate, the plurality of layers are patterned, and multiple dielectric layers and conductive materials are deposited over the CZT material. Another layer of CZT material encapsulates the conductive material.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Li Huang, Chi-Cheng Chen, Hon-Lin Huang, Chien-Chih Chou, Chin-Yu Ku, Chen-Shien Chen
  • Patent number: 10083954
    Abstract: A semiconductor device may be provided. The semiconductor device may include a first guard ring disposed in a first region, and a second guard ring disposed in a second region. The semiconductor device may include a first metal line and a second metal line respectively disposed over the first guard ring and the second guard ring, and respectively coupled to the first guard ring and the second guard ring. The semiconductor device may include a gate pattern coupled to the first metal line or the second metal line, wherein the first metal line and the second metal line are configured to respectively receive a first voltage and a second voltage. The second voltage may have a different potential from the first voltage.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: September 25, 2018
    Assignee: SK hynix Inc.
    Inventor: Wang Su Kim
  • Patent number: 10084118
    Abstract: A semiconductor light-emitting device includes: a package substrate having a mounting surface on which a first circuit pattern and a second circuit pattern are disposed; a semiconductor LED chip mounted on the mounting surface, having a first surface which faces the mounting surface and on which a first electrode and a second electrode are disposed, a second surface opposing the first surface, and side surfaces located between the first surface and the second surface, the first electrode and the second electrode being connected to the first circuit pattern and the second circuit pattern, respectively; a wavelength conversion film disposed on the second surface; and a side surface inclined portion disposed on the side surfaces of the semiconductor LED chip, providing inclined surfaces, and including a light-transmitting resin containing a wavelength conversion material.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: September 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mi Jeong Yun, Jong Sup Song
  • Patent number: 10084013
    Abstract: A thin-film transistor includes a substrate, a gate electrode formed on a surface of the substrate, a gate protection layer and a semiconductor layer stacked on the gate electrode, and an etch stop layer, source terminal metal, and drain terminal metal formed on a surface of the semiconductor layer in such a way that the source terminal metal and the drain terminal metal are respectively located on two opposite sides of the etch stop layer. The thin-film transistor further includes a light shielding layer, an insulation medium layer, and a pixel electrode. The light shielding layer is stacked on the etch stop layer to prevent light from irradiating the semiconductor layer. The insulation medium layer covers the source terminal metal, the drain terminal metal, and the light shielding layer. The pixel electrode is formed on a surface of the insulation medium layer and electrically connected to the drain terminal metal.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: September 25, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Qiuping Huang
  • Patent number: 10084063
    Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Jiun Kuang, Yi-Han Wang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Patent number: 10062687
    Abstract: A semiconductor device includes a semiconductor substrate, an interlayer dielectric layer on the semiconductor substrate, a capacitor on the interlayer dielectric layer, and a PN-junction diode in the semiconductor substrate and below the capacitor. The PN-junction diode includes a p-type ion implanted region and an n-well located below the p-type ion implanted region and completely surrounding the p-type ion implanted region. The PN-junction diode in the semiconductor substrate may prevent noise from entering the capacitor to improve the noise immunity of the semiconductor device.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: August 28, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Deng-Ping Yin