Patents Examined by Tuan V. Thai
  • Patent number: 10417125
    Abstract: The disclosed embodiments provide a method, apparatus, and system for selecting, based on feedback from previous garbage collections, a portion of a referenced memory area for garbage collection within a time window. During the execution of a software program, the system selects a given portion of a referenced memory area on which garbage collection can be completed within the given time window and attempts to complete garbage collection on at least the given portion of the referenced memory area before the end of the given time window. Next, the system selects, based on the results of the garbage collection performed during the given time window, a subsequent portion of the referenced memory area on which garbage collection can be completed within the subsequent time window and attempts to complete garbage collection on at least the subsequent portion of the referenced memory area before the end of the subsequent time window.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: September 17, 2019
    Assignee: Oracle International Corporation
    Inventors: Thomas Schatzl, Nils Mikael Gerdin, Erik Gustav Helin
  • Patent number: 10417138
    Abstract: Provided are a computer program product, system, and method for considering a frequency of access to groups of tracks and density of the groups to select groups of tracks to destage. One of a plurality of densities for one of a plurality of groups of tracks is incremented in response to determining at least one of that the group is not ready to destage and that one of the tracks in the group in the cache transitions to being ready to destage. A determination is made of a group frequency indicating a frequency at which tracks in the group are modified. At least one of the density and the group frequency is used for each of the groups to determine whether to destage the group. The tracks in the group in the cache are destaged to the storage in response to determining to destage the group.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: September 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Lokesh M. Gupta
  • Patent number: 10409509
    Abstract: A memory management service occupies a configurable portion of an overall memory system in a disaggregate compute environment. The service provides optimized data organization capabilities over the pool of real memory accessible to the system. The service enables various types of data stores to be implemented in hardware, including at a data structure level. Storage capacity conservation is enabled through the creation and management of high-performance, re-usable data structure implementations across the memory pool, and then using analytics (e.g., multi-tenant similarity and duplicate detection) to determine when data organizations should be used. The service also may re-align memory to different data structures that may be more efficient given data usage and distribution patterns. The service also advantageously manages automated backups efficiently.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: September 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: John Alan Bivens, Koushik K. Das, Min Li, Ruchi Mahindru, Harigovind V. Ramasamy, Yaoping Ruan, Valentina Salapura, Eugen Schenfeld
  • Patent number: 10402093
    Abstract: A distributed electronic storage system (DESS) comprises congestion management circuitry and data migration circuitry. The congestion management circuitry is operable to determine an amount of congestion in the DESS. The data migration circuitry is operable to control migration of data stored in a first tier of storage to a second tier of storage based on the amount of congestion in the DESS, characteristics of the data, and characteristics of the first tier of storage.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: September 3, 2019
    Assignee: Weka.IO LTD
    Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel, Kanael Arditti, Tomer Filiba
  • Patent number: 10397139
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 27, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki, Yoshifumi Nishi, Takao Marukame, Takahiro Kurita
  • Patent number: 10394453
    Abstract: Example embodiments of the present invention relate to methods, systems, and a computer program product for storing data compressed according to available system resources. The method includes evaluating system resources of a data storage system and selecting a compression algorithm according to the system resources. The data set then may be compressed according to the selected compression algorithm and the compressed data stored in the data storage system.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: August 27, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Ron Bigman
  • Patent number: 10394710
    Abstract: An SCM memory mode NVDIMM-N cache system includes an SCM subsystem, and an NVDIMM-N subsystem having at volatile memory device(s) and non-volatile memory device(s). A memory controller writes data to the volatile memory device(s) and, in response, updates a cache tracking database. The memory controller then writes a subset of the data to the SCM subsystem subsequent to the writing of that data to the volatile memory device(s) and, in response, updates the cache tracking database. The memory controller then receives a shutdown signal and, in response, copies the cache tracking database to the volatile memory device(s) in the NVDIMM-N subsystem. The NVDIMM-N subsystem then copies at least some of the data and the cache tracking database from the volatile memory device(s) to the non-volatile memory device(s) prior to shutdown. The data and the cache tracking database may then be retrieved from non-volatile memory device(s) when the system is restored.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: August 27, 2019
    Assignee: Dell Products L.P.
    Inventors: Stuart Allen Berke, John E. Jenne
  • Patent number: 10387038
    Abstract: The present disclosure includes apparatus, systems, computer readable storage media and techniques relating to virtualization of data storage space. In one aspect, a method performed by a data processing device includes identifying a subset of physical disks within a node. The identified subset includes at least one of the physical disks having at least one subdisk with free storage space. The node includes processing units and the physical disks arranged to form at least one group. A priority value is assigned to the identified subset of the physical disks. The identified subset of the physical disks is sorted based on the assigned priority value, and subdisks are selected from the sorted subset of the physical disks to form a logical disk.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: August 20, 2019
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Haim Bitner, Sanjyot Tipnis, Abhijeet P. Gole
  • Patent number: 10387332
    Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: August 20, 2019
    Assignee: Mellanox Technologies Ltd.
    Inventors: Christopher D. Metcalf, Bruce Edwards, Anant Agarwal, Chyi-Chang Miao, Patrick Robert Griffin
  • Patent number: 10387329
    Abstract: Profiling cache replacement is a technique for managing data migration between a main memory and a cache memory to improve overall system performance. A profiler maintains counters that count memory requests for access to the pages maintained in both the cache memory and the main memory. Based on this access-request count information, a mover moves pages between the main and cache memories. For example, the mover can swap little-requested pages of the cache memory with highly-requested pages of the main memory. The mover can do so, for instance, when the counters indicate that the number of page access requests for highly-requested pages of the main memory is greater than the number of page access requests for little-requested pages of the cache memory. To avoid impeding the operations of memory users, the mover can perform page swapping in the background at predetermined time intervals, such as once every microsecond (?s).
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: August 20, 2019
    Assignee: Google LLC
    Inventor: Chih-Chung Chang
  • Patent number: 10380022
    Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: August 13, 2019
    Assignee: Netlist, Inc.
    Inventors: Hyun Lee, Jayesh R. Bhakta, Chi She Chen, Jeffery C. Solomon, Mario Jesus Martinez, Hao Le, Soon J. Choi
  • Patent number: 10379747
    Abstract: A method includes receiving, by a hardware controller of a storage device and from a host device, a command to read data from or write data to a non-volatile memory device of the storage device. The method includes, responsive to receiving the command: initializing, by firmware executing at a processor of the hardware controller, a command to retrieve data from or write data to the non-volatile memory device; determining, by circuit logic of the hardware controller, a time indicative of when the firmware initialized the command; determining, by the circuit logic, a time indicative of when the command terminated; and storing, by the circuit logic and at a latency monitoring cache of the storage device, a timestamp associated with the time indicative of when the command was initialized and a timestamp associated with the time indicative of when the command terminated.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 13, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mark David Erickson, Adam Christopher Geml, Darin Edward Gerhart, Nicholas Edward Ortmeier
  • Patent number: 10372334
    Abstract: One embodiment provides a method for reclaiming free space. The method comprises selecting a first blob for reclamation from a first data center; sending a first message to a second data center indicating the first blob is to be reclaimed; sending a second message to the second data center after reclaiming the first blob; receiving a global reclamation complete message from the second data center; reading at least one data set from the first blob; and storing in a write buffer the at least one data set for encoding into a erasure code group in an alternative blob in the first data center. Further, upon receipt of the global reclamation message from the second data center, indicating the first blob is free in the map in the first data center. In one embodiment, selecting the first blob is based on the map indicating free space in the first data center.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Hetzler, Wayne C. Hineman
  • Patent number: 10359934
    Abstract: Example embodiments of the present invention relate to a method, an apparatus, and a computer program product for IT appliance control. The method comprises determining an action regarding a storage system, encoding the action regarding the storage system, and representing the action regarding the storage system as a graphical representation.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: July 23, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Vitaly Kozlovsky, Inga Petryaevskaya, Yuri Zagrebin, Konstantin Tyapochkin, Alexey Fomin
  • Patent number: 10360168
    Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: July 23, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Patrick Robert Griffin, Carl G. Ramey
  • Patent number: 10353587
    Abstract: A method of operating a data storage device includes fetching a first plurality of commands from at least one submission queue generated in a host memory, determining whether a ratio of a second plurality of commands from among the fetched first plurality of commands exceeds a reference ratio, and adjusting a number of a plurality of pointers being fetched at substantially a same time based on determining whether the ratio exceeds the reference ratio. The second plurality of commands has a same property, the plurality of pointers indicates a physical address of the host memory corresponding to the first plurality of commands, and the data storage device includes a storage controller configured to perform an interfacing operation with a host including the host memory.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: July 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taemin Jeong, Soonjae Won
  • Patent number: 10353625
    Abstract: The memory system may include a memory device including: a plurality of planes each including a plurality of memory blocks suitable for storing data, and a plurality of page buffers corresponding to the planes; and a controller including a memory, the controller being suitable for performing a read operation to the memory blocks of a first plane storing a first data corresponding to a read command among the planes by referring to a meta-data of the first data, and for providing the first data to a host; wherein the meta-data is stored in the memory or the page buffers.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: July 16, 2019
    Assignee: SK hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 10353588
    Abstract: In a data storage system a host I/O request is received from a host-side interface, the host I/O request specifying a range of logical block addresses (LBAs) of a mapped logical unit (MLU). Mapping information is obtained for a plurality of extents of the underlying logical units of storage. If there are a sufficient number of free sub-I/O request tracking structures to track completion of a plurality of respective sub-I/O requests for the extents, then the sub-I/O requests are concurrently issued to the device-side interface, using the mapping information. Upon receiving transfer initiation responses for the sub-I/O requests to initiate transfer of the respective extents, they are forwarded to the host-side interface to cause the respective extents to be transferred to/from the host. As the transfer initiation responses are forwarded to the host-side interface, the respective sub-I/O request tracking structures are freed for use in processing subsequent host I/O requests.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 16, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Milind Koli, Timothy C. Ng
  • Patent number: 10353600
    Abstract: A method for verification of content of tape cartridges in a tape library system using tape drives of the tape library, is provided. The method includes instructing the tape drive to perform tape cartridge verification on the tape cartridge. The method further includes after completion of the tape cartridge verification, unloading the tape cartridge to its original storage position. The method further includes transmitting verification data of the tape cartridge verification to a database of the tape library system for analysis.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bernd Freitag, Frank Krick, Tim Oswald, Harald Seipp
  • Patent number: 10347346
    Abstract: Embodiments herein describe a memory system that queues program requests to a block of flash memory until a predefined threshold is reached. That is, instead of performing program requests to write data into the block as the requests are received, the memory system queues the requests until the threshold is satisfied. Once the buffer for the block includes the threshold amount of program requests, the memory system performs the stored requests. In one embodiment, the memory system erases all the pages in the block before writing the new data in the program requests into the destination pages. The data that was originally stored in the pages that are not destination pages is rewritten into the pages. In this example, the queued program requests can be written into the pages using one erase and write step rather than individual erase and write steps for each of the requests.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Saravanan Sethuraman, Gary A. Tressler, Harish Venkataraman