Patents Examined by Tuan V. Thai
  • Patent number: 11327890
    Abstract: A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for multiple cores, and can optionally serve as a point of serialization of the memory subsystem. A low-level cache is partitionable into partitions that are subsets of both ways and sets, and each partition can serve an independent process and/or processor core.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: May 10, 2022
    Assignee: MARVELL ASIA PTE, LTD.
    Inventor: Shubhendu S. Mukherjee
  • Patent number: 11314658
    Abstract: A data processing apparatus comprises processing circuitry to execute a plurality of processes. An ownership table comprises one or more entries each indicating, for a corresponding block of physical addresses, which of the processes is an owner process that has exclusive control of access to the corresponding block of physical addresses. A new process may be prevented from becoming an owner process until after successful completion of destructive overwriting. Ownership protection circuitry may detect a mismatch between an expected attribute, which is dependent on information in a page table entry, and an attribute specified in the ownership table. Each entry in the ownership table, for example, may indicate a level of encryption to be applied. Access control circuitry such as a memory management unit (MMU) may also determine whether an access request satisfies access permissions. The ownership table may also specify whether a higher privilege level process is allowed to access a block of physical addresses.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 26, 2022
    Assignee: Arm Limited
    Inventors: Jason Parker, Richard Roy Grisenthwaite, Andrew Christopher Rose
  • Patent number: 11314664
    Abstract: A memory access device includes: a data processor configured to output an access request requesting access to a memory connected to a data bus, perform a data processing on data in the accessed memory, and provide notification of a progress status of the data processing; a priority switching control part configured to determine an urgency of the data processing by the data processor according to the progress status of the data processing notified from the data processor, and output a priority switching signal notifying switching of a priority of the data processor; and a bus arbiter connected to the data bus, configured to change the priority of the data processor according to the priority switching signal to arbitrate the access request output from the data processor, and control access to the memory according to the access request that has been arbitrated.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 26, 2022
    Assignee: OLYMPUS CORPORATION
    Inventors: Shinsuke Homma, Kazue Chida, Akira Ueno
  • Patent number: 11307958
    Abstract: Data collection is provided, in which one or more affected transactions related to one or more transaction exceptions are determined. Based on one or more features of the one or more affected transactions, one or more trace features are determined. Based on the one or more trace features, a data collection rule is generated. Data of a subsequent transaction complying with the data collection rule is collected.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: April 19, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Zheng, Si Bin Fan, Xue Yong Zhang, Li Xiang, Li Li, Ting Xie, Chang Zhi GZ Zhang, Yan Wang, Hai He
  • Patent number: 11301135
    Abstract: The data management device capable of calculating an evaluation index based on the sensor data includes: a sensor data acquisition unit that acquires the sensor data from one or more sensors installed in an industrial machine; an evaluation index calculation unit that calculates the evaluation index with use of the sensor data; a sensor data storage unit that saves the sensor data; and a sensor data deletion unit that deletes the sensor data when a total volume of the sensor data in the sensor data storage unit exceeds an upper limit. The sensor data deletion unit determines saving priority of the sensor data based on a degree of change in the evaluation index and deletes the sensor data in accordance with the saving priority.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: April 12, 2022
    Assignee: FANUC CORPORATION
    Inventors: Kazuhiro Satou, Kazunori Iijima
  • Patent number: 11294824
    Abstract: Aspects of a storage device including a memory and a controller are provided which allows for reduced latency of read-modify-write operations when a data length from a host is unaligned at two ends with a write length of the controller. When the controller receives from a host device a write command for data, the controller performs a first read of a head portion and a second read of a tail portion immediately after performing the first read. The controller performs a single L2P translation of one of the head or tail portions, senses the data associated with the head and tail portions once into latches, and reads the data from the latches for both the head and tail portions without performing another data sense. The controller then writes the data in response to the write command after performing the first read and the second read.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: April 5, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dhanunjaya Rao Gorrle, Hongmei Xie, Hyuk Il Kwon
  • Patent number: 11294823
    Abstract: An electronic system such as an imaging system may include processing circuitry and memory circuitry. Data replacement circuitry may be interposed between the processing circuitry and the memory circuitry. In some implementations, the memory circuitry may be a read-only memory, and data replacement circuitry may be used to selectively replace executable firmware instructions stored on the read-only memory. The selective replacement operations may be based on an address that processing circuitry provides to access the memory circuitry. The data replacement circuitry may be implemented separately from the processing circuitry and the memory circuitry and may include a comparator block, registers, and switching circuitry.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: April 5, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Peter Michael Hall
  • Patent number: 11294575
    Abstract: A method for verification of content of tape cartridges in a tape library system using tape drives of the tape library, is provided. The method includes instructing the tape drive to perform tape cartridge verification on the tape cartridge. The method further includes after completion of the tape cartridge verification, unloading the tape cartridge to its original storage position. The method further includes transmitting verification data of the tape cartridge verification to a database of the tape library system for analysis.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: April 5, 2022
    Assignee: International Business Machines Corporation
    Inventors: Bernd Freitag, Frank Krick, Tim Oswald, Harald Seipp
  • Patent number: 11288195
    Abstract: A data processing system comprises a requesting node; a home node to control coherency amongst data stored by the data processing system; and one or more further nodes, at least one of the further nodes having a memory; the requesting node being configured to issue a data handling transaction to the home node, the data handling transaction defining a data handling operation relating to a range of memory addresses, the requesting node being configured to maintain an address hazard at the requesting node inhibiting issue of another data handling transaction for that range of memory addresses until the requesting node is notified by the home node that the data handling transaction has completed; the home node being configured, in response to the data handling transaction, to issue one or more data handling instructions to cause one or more given nodes of the one or more further nodes to perform the data handling operation, the home node being configured to notify completion to the requesting node in response to
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: March 29, 2022
    Assignee: Arm Limited
    Inventor: Andrew David Tune
  • Patent number: 11287979
    Abstract: A distributed electronic storage system (DESS) comprises congestion management circuitry and data migration circuitry. The congestion management circuitry is operable to determine an amount of congestion in the DESS. The data migration circuitry is operable to control migration of data stored in a first tier of storage to a second tier of storage based on the amount of congestion in the DESS, characteristics of the data, and characteristics of the first tier of storage.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: March 29, 2022
    Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel, Kanael Arditti, Tomer Filiba
  • Patent number: 11288136
    Abstract: Configuring parameters in backup environments is described. A system outputs, via a user interface, a backup environment question. The system receives, via the user interface, an answer to the backup environment question. The system configures a backup environment parameter based on the answer to the backup environment question and based on information extracted from a corresponding backup environment.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: March 29, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Balaji Panchanathan, Pravin Kumar Ashokkumar, Satchidananda Patra
  • Patent number: 11281592
    Abstract: Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: March 22, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Russell J. Schreiber
  • Patent number: 11281384
    Abstract: A method comprises determining, in a process of storing data for a computing task of a first dedicated processing resource of a set of dedicated processing resources to the first dedicated processing resource, a size of an available space of a memory of the first dedicated processing resource; in response to the size of the available space of the memory of the first dedicated processing resource being lower than a predetermined threshold value, determining a second dedicated processing resource of the set of dedicated processing resources, a size of an available space of a memory of the second dedicated processing resource is greater than the predetermined threshold value; and causing at least one portion of the data not stored on the memory of the first dedicated processing resource to be stored on the memory of the second dedicated processing resource.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: March 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Junping Zhao, Kun Wang
  • Patent number: 11275701
    Abstract: Various embodiments include methods and systems performed by a processor of a first function block for providing secure timer synchronization with a second function block. Various embodiments may include storing, in a shared register space, a first time counter value in which the first time counter value is based on a global counter of the second function block, transmitting, from the shared register space, the stored first time counter value to a preload register of the first function block, receiving, by the first function block, a strobe signal from the second function block configured to enable the first time counter value in the preload register to be loaded into a global counter of the first function block, and configuring the global counter with the first time counter value from the preload register.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: March 15, 2022
    Assignee: QUALCOMM Incorporated
    Inventor: Naveen Kumar Narala
  • Patent number: 11275508
    Abstract: Methods for automatically performing a background operation in a memory device might include automatically performing the background operation responsive to automatic performance of the background operation being enabled and receiving a start command.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Francesco Falanga, Danilo Caraccio
  • Patent number: 11269532
    Abstract: A technique for managing data storage begins at a predetermined offset relative to a chunk of data received for writing, and identifies a span of contiguous regions of the chunk that contain identical data. The technique replaces the span of contiguous regions of the chunk with a single instance of a region of the contiguous regions. The technique persistently stores a shortened version of the chunk with the single instance replacing the span of contiguous regions.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: March 8, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Uri Shabi, Amitai Alkalay
  • Patent number: 11256436
    Abstract: Systems and methods for balancing multiple partitions of non-volatile memory devices are provided. Embodiments discussed herein execute a balance proportion scheme in connection with a NVM that is partitioned to have multiple partition types. Each partition type has an associated endurance that defines an average number of program/erase (P/E) cycles it can endure before it reaches failure. For example, a first partition type may have a substantially greater endurance than a second partition type. The balance proportion scheme ensures that, even though each partition type has a different associated endurance, all partition types are used proportionally with respect to each other to balance their respective P/E cycles. This way, both partition types will reach the upper limits of their respective endurance levels out at approximately the same time.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: February 22, 2022
    Assignee: Apple Inc.
    Inventors: Alexander Paley, Andrew W. Vogan
  • Patent number: 11257552
    Abstract: A memory device includes a memory cell array and a memory controller. The memory cell array includes a plurality of memory blocks. Each of the memory blocks includes a plurality of word lines. A plurality of memory chunks is coupled to at least one of the word lines. The memory controller is configured to program data to a particular memory chunk of the plurality of memory chunks by performing a chunk operation that includes selecting a particular word line from the plurality of word lines, selecting a particular memory chunk from the plurality of memory chunks that are coupled to the particular word line, and applying a program voltage to a particular memory block corresponding to the particular memory chunk to program data to the particular memory chunk.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: February 22, 2022
    Assignee: Macronix International Co., Ltd.
    Inventor: Yi-Chun Liu
  • Patent number: 11249679
    Abstract: A request to write data at the memory component is received. Responsive to receiving the request to write the data at the memory component, a random value is determined. A first write operation mode from multiple write operations modes is selected based on the random value. A write operation to write the data at the memory component is performed in accordance with the first write operation mode.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 15, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Zhenlei Shen, Fangfang Zhu, Tingjun Xie, Jiangli Zhu
  • Patent number: 11249909
    Abstract: Systems and methods to predict and prefetch a cache access based on a delta pattern are disclosed. The delta pattern may comprise a sequence of differences between first and second cache accesses within a page. In one example, a processor includes execution circuitry to extract a delta history corresponding to a delta pattern associated with one or more previous cache accesses corresponding to a page of memory. The processor execution circuitry further generates a bucketed delta history based on the delta history corresponding to the page of memory and selects a prediction entry based on the bucketed delta history. The processor execution circuitry then identifies one or more prefetch candidates based on a confidence threshold, with the confidence threshold indicating one or more probable delta patterns, and filters the one or more prefetch candidates. Prefetch circuitry of the processor then predicts and prefetches a cache access based the one or more prefetch candidates.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventors: Hanna Alam, Joseph Nuzman