Patents Examined by Tucker J Wright
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Patent number: 11605607Abstract: In an embodiment, a method includes forming a conductive feature adjacent to a substrate; treating the conductive feature with a protective material, the protective material comprising an inorganic core with an organic coating around the inorganic core, the treating the conductive feature comprising forming a protective layer over the conductive feature; and forming an encapsulant around the conductive feature and the protective layer. In another embodiment, the method further includes, before forming the encapsulant, rinsing the protective layer with water. In another embodiment, the protective layer is selectively formed over the conductive feature.Type: GrantFiled: March 19, 2021Date of Patent: March 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Chun Cho, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
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Patent number: 11600608Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.Type: GrantFiled: March 17, 2021Date of Patent: March 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jichul Kim, Chajea Jo, Sang-Uk Han, Kyoung Soon Cho, Jae Choon Kim, Woohyun Park
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Patent number: 11594525Abstract: A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.Type: GrantFiled: May 23, 2022Date of Patent: February 28, 2023Assignee: Micron Technology, Inc.Inventors: Tongbi Jiang, Yong Poo Chia
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Patent number: 11594565Abstract: An image sensor is disclosed. In some implementations, the image sensor includes a substrate including one or more photoelectric conversion elements arranged in the substrate and structured to convert light into electrical signals representing an image carried by the light, and a plurality of metal layers arranged at different distances from a surface of the substrate and located below the one or more photoelectric conversion elements, each of the metal layers including one or more metal patterns. The one or more metal patterns of the plurality of metal layers are arranged in a concave shape facing the photoelectric conversion element such that incident light reflected by metal layers converges toward the photoelectric conversion element.Type: GrantFiled: August 12, 2020Date of Patent: February 28, 2023Assignee: SK HYNIX INC.Inventor: Kyung Su Byun
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Patent number: 11587844Abstract: Electronic device package on package (POP) technology is disclosed. A POP can comprise a first electronic device package including a heat source. The POP can also comprise a second electronic device package disposed on the first electronic device package. The second electronic device package can include a substrate having a heat transfer portion proximate the heat source that facilitates heat transfer from the heat source through a thickness of the substrate. The substrate can also have an electronic component portion at least partially about the heat transfer portion that facilitates electrical communication. In addition, the POP can comprise an electronic component operably coupled to the electronic component portion.Type: GrantFiled: July 2, 2016Date of Patent: February 21, 2023Assignee: Intel CorporationInventors: Eng Huat Goh, Jiun Hann Sir, Min Suet Lim, Xi Guo
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Patent number: 11581299Abstract: Techniques and architecture are disclosed for a method for making a custom circuit comprising forming a common wafer template, selecting at least two elements of the common wafer template to be chosen elements, and adding at least one metal layer to interconnect the chosen elements to form a circuit. The common wafer template includes a plurality of transistors, a plurality of resistors, a plurality of capacitors, and a plurality of bond pads. Final circuit customization of the common wafer template is accomplished by adding at least one metal layer that forms interconnects to passive and active elements in the template in order to complete the circuit.Type: GrantFiled: March 12, 2020Date of Patent: February 14, 2023Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Carlton T. Creamer, Daniel C. Boire, Kanin Chu, Hong M. Lu, Bernard J. Schmanski
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Patent number: 11574943Abstract: A semiconductor package is provided. The package includes a semiconductor chip that includes photoelectric conversion elements provided on an active array region of the semiconductor chip; a transparent member on the semiconductor chip; and a spacer between the semiconductor chip and the transparent member, and horizontally spaced apart from the active array region. The spacer includes: a supporter that extends from a top surface of the semiconductor chip toward a bottom surface of the transparent member; a first adhesive pattern that is between the semiconductor chip and a bottom surface of the supporter; and a second adhesive pattern that is between the transparent member a top surface of the supporter. The spacer protrudes from a lateral surface of the semiconductor chip, and a lateral surface of the spacer is offset from the lateral surface of the semiconductor chip.Type: GrantFiled: August 18, 2020Date of Patent: February 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Kyongsoon Cho
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Patent number: 11569212Abstract: Aspects of the disclosure relate to a semiconductor device power management system including a semiconductor device of a set of semiconductor devices provided on a substrate, wherein the semiconductor device includes an independent power supply unit.Type: GrantFiled: November 9, 2017Date of Patent: January 31, 2023Assignee: INTERNATIONAL FRONTIER TECHNOLOGY LABORATORY, INC.Inventors: Nobuaki Komatsu, Tomoko Ito
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Patent number: 11563049Abstract: Provided are a solid-state imaging apparatus, a method for manufacturing a solid-state imaging apparatus, and an electronic apparatus equipped with a solid-state imaging apparatus that can reduce the size of a semiconductor chip in such a way that one semiconductor substrate having a logic circuit controls two sensors. Provided is a solid-state imaging apparatus including a first sensor, a first semiconductor substrate having a memory, a second semiconductor substrate having a logic circuit, and a second sensor, in which the first sensor, the first semiconductor substrate, the second semiconductor substrate, and the second sensor are arranged in this order.Type: GrantFiled: March 5, 2019Date of Patent: January 24, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Kenichi Nishizawa
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Patent number: 11557552Abstract: A voltage-reference plane has gradient regions that provide altered thicknesses that are useful in a power-deliver network for a semiconductor package substrate. Different signal trace types are located over various portions of the gradient regions to facilitate signal integrity.Type: GrantFiled: March 13, 2020Date of Patent: January 17, 2023Assignee: Intel CorporationInventors: Chin Lee Kuan, Jackson Chung Peng Kong, Bok Eng Cheah
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Patent number: 11552053Abstract: Optical sensor modules and methods of fabrication are described. In an embodiment, an optical component is mounted on a module substrate. In an embodiment, a pillar of stacked wireballs adjacent the optical component is used for vertical connection between the module substrate and a top electrode pad of the optical component.Type: GrantFiled: June 25, 2020Date of Patent: January 10, 2023Assignee: Apple Inc.Inventors: Bilal Mohamed Ibrahim Kani, Kishore N. Renjan, Kyusang Kim, Manoj Vadeentavida, Pierpaolo Lupo, Praveesh Chandran
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Patent number: 11552039Abstract: The present disclosure relates to an embedded packaging module comprising a first semiconductor device, a first packaging layer and a first wiring layer, the first semiconductor device having a first and a second face, at least two positioning bulges and at least one bonding pad being provided on the first face of the first semiconductor device; the first packaging layer being formed on both the first face and a surface adjacent to the first face, the positioning bulges being positioned in the first packaging layer, at least one first via hole being provided in the first packaging layer, the bottom of the first via hole being positioned in the bonding pad and contacting with the bonding pad; the first wiring layer being positioned on the side of the first packaging layer away from the first semiconductor device and being electrically connected with the bonding pad through the first via hole.Type: GrantFiled: December 30, 2019Date of Patent: January 10, 2023Assignee: Delta Electronics (Shanghai) CO., LTDInventors: Zengsheng Wang, Xuetao Guo, Kai Lu, Hui Li
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Patent number: 11545457Abstract: A semiconductor package, a redistribution structure and a method for forming the same are provided. The redistribution structure for coupling an encapsulated die is provided, the redistribution structure includes a conductive pattern disposed over and electrically coupled to the encapsulated die. The conductive pattern extends beyond an edge of the encapsulated die along a first extending direction which intersects a second extending direction of the edge of the encapsulated die by an angle in a top view, and an impurity concentration of sulfur in the conductive pattern is less than about 0.1 ppm.Type: GrantFiled: August 30, 2020Date of Patent: January 3, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiang-Hao Lee, Hung-Jui Kuo, Ming-Che Ho
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Patent number: 11545459Abstract: A semiconductor device includes a semiconductor die attached to a substrate and a metal clip attached to a side of the semiconductor die facing away from the substrate by a soldered joint. The metal clip has a plurality of slots dimensioned so as to take up at least 10% of a solder paste reflowed to form the soldered joint. Corresponding methods of production are also described.Type: GrantFiled: January 22, 2021Date of Patent: January 3, 2023Assignee: Infineon Technologies AGInventors: Thomas Stoek, Michael Stadler, Mohd Hasrul Zulkifli
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Patent number: 11538841Abstract: An image sensing device is provided to include a semiconductor substrate configured to include a photoelectric conversion element that generates photocharges in response to light incident to the photoelectric conversion element, a plurality of microlenses disposed over the semiconductor substrate and configured to allow the incident light to converge upon the photoelectric conversion element, and a polarization structure disposed between the semiconductor substrate and the microlenses and configured to transmit light of a polarization oriented in a specific direction to the photoelectric conversion element, wherein the polarization structure includes one or more air layers.Type: GrantFiled: July 28, 2020Date of Patent: December 27, 2022Assignee: SK HYNIX INC.Inventor: Min Su Cho
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Patent number: 11532726Abstract: A VDMOS device and a manufacturing method therefor.Type: GrantFiled: December 14, 2020Date of Patent: December 20, 2022Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.Inventor: Zheng Bian
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Patent number: 11527569Abstract: A pixel cell includes a plurality of subpixels to generate image charge in response to incident light. The subpixels include an inner subpixel laterally surrounded by outer subpixels. A first plurality of transfer gates disposed proximate to the inner subpixel and a first grouping of outer subpixels. A first floating diffusion is coupled to receive the image charge from the first grouping of outer subpixels through a first plurality of transfer gates. A second plurality of transfer gates disposed proximate to the inner subpixel and the second grouping of outer subpixels. A second floating diffusion disposed in the semiconductor material and coupled to receive the image charge from each one of the second grouping of outer subpixels through the second plurality of transfer gates. The image charge in the inner subpixel is received by the first, second, or both floating diffusions through respective transfer gates.Type: GrantFiled: May 18, 2020Date of Patent: December 13, 2022Assignee: OmniVision Technologies, Inc.Inventors: Duli Mao, Bill Phan, Keiji Mabuchi, Seong Yeol Mun, Yuanliang Liu, Vincent Venezia
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Patent number: 11515435Abstract: A semiconductor device includes a semiconductor substrate, a photo sensing region, and a plurality of nanostructures. The semiconductor substrate has a first dopant. The photo sensing region is embedded in the semiconductor substrate, has a top surface level with a top surface of the semiconductor substrate, and has a second dopant that is of a different conductivity type than the first dopant. The plurality of nanostructures is on the photo sensing region and is made of a material the same as the photo sensing region.Type: GrantFiled: October 9, 2020Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Hsiang Tseng, Chih-Fei Lee, Chia-Pin Cheng, Fu-Cheng Chang
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Patent number: 11508645Abstract: An integrated circuit assembly including a first die including a device side and a backside opposite the device side; and a second die including a plurality of fluidly accessible channels therein, wherein the second die is coupled to a backside of the first die. A method of fabricating an integrated circuit assembly including coupling a first die to a second die, wherein the first die includes a device side and an opposite backside, wherein the device side includes a plurality of integrated circuits and wherein the second die includes a plurality of fluidly accessible channels therein.Type: GrantFiled: September 29, 2017Date of Patent: November 22, 2022Assignee: Intel CorporationInventors: Chandra M. Jha, Je-Young Chang
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Patent number: 11508739Abstract: A method of manufacturing a memory structure including the following steps is provided. A first pad layer is formed on a substrate. Isolation structures are formed in the first pad layer and the substrate. At least one shape modification treatment is performed on the isolation structures. Each shape modification treatment includes the following steps. A first etching process is performed on the first pad layer to reduce a height of the first pad layer and to form first openings exposing sidewalls of the isolation structures. After the first etching process is performed, a second etching process is performed on the isolation structures to modify shapes of the sidewalls of the isolation structures exposed by the first openings. The first pad layer is removed to form a second opening between two adjacent isolation structures.Type: GrantFiled: May 21, 2020Date of Patent: November 22, 2022Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Hui-Chin Huang, Kai-Yao Shih, Yu-Mei Liao, Hsin-Yi Liao