Patents Examined by Uyen Smet
  • Patent number: 11120859
    Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be selected using a selection component that is in electronic communication with a sense amplifier and a ferroelectric capacitor of a ferroelectric memory cell. A voltage applied to the ferroelectric capacitor may be sized to increase the signal sensed during a read operation. The ferroelectric capacitor may be isolated from the sense amplifier during the read operation. This isolation may avoid stressing the ferroelectric capacitor which may otherwise occur due to the applied read voltage and voltage introduce by the sense amplifier during the read operation.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 11120883
    Abstract: A semiconductor storage device includes a first semiconductor extending above a substrate and including a first part and a second part, a first word line at a first level above the substrate and facing the first part of the first semiconductor, a second word line at the first level above the substrate and facing the second part of the first semiconductor, a first cell transistor including a first area of the first part of the first semiconductor that faces the first word line, and a second cell transistor including a second area of the second part of the first semiconductor that faces the second word line, wherein during an operation of reading data from the first cell transistor, a first voltage that is less than a threshold voltage of the second cell transistor and greater than or equal to zero voltage is applied to the second word line.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: September 14, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Takuya Futatsuyama, Masanobu Shirakawa
  • Patent number: 11120870
    Abstract: Methods, systems, and devices for multi-deck memory arrays are described. A multi-deck memory device may include a memory array with a cell having a self-selecting memory element and another array with a cell having a memory storage element and a selector device. The device may be programmed to store multiple combinations of logic states using cells of one or more decks. Both the first deck and second deck may be coupled to at least two access lines and may have one access line that is a common access line, coupling the two decks. Additionally, both decks may overlie control circuitry, which facilitates read and write operations. The control circuitry may be configured to write a first state or a second state to one or both of the memory decks via the access lines.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Andrea Redaelli, Innocenzo Tortorelli, Agostino Pirovano, Fabio Pellizzer
  • Patent number: 11107528
    Abstract: In some embodiments, the present disclosure relates to a method, comprising the performing of a reset operation to a resistive random access memory (RRAM) cell. A first voltage bias having a first polarity is applied to the RRAM cell. An absolute value of the first voltage bias is greater than an absolute value of a first reset voltage. The application of the first voltage bias induces the RRAM cell to change from a low resistance to an intermediate resistance greater than the low resistance. A second voltage bias having a second polarity oppose to the first polarity is then applied to the RRAM cell. An absolute value of the second reset voltage is less than an absolute value of the second voltage bias and less than the absolute value of the first reset voltage. The application of the second voltage bias induces the RRAM cell to have a high resistance.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Yang Chen, Cheng-Jun Wu, Chun-Yang Tsai, Kuo-Ching Huang
  • Patent number: 11087800
    Abstract: A sense amplifier architecture is presented that can reduce sensing times by being able to sense smaller voltage swings between an ON memory cell and an OFF memory cell. The sense amplifier includes a sensing capacitor that, on one side, is connectable to multiple bit lines and, on the other side, to a main sense amplifier section. The main section includes a latch formed of a pair of inverters that has an input connected to the capacitor and an output that is connected to the other side of the capacitor by a third inverter. To pre-charge the latch, the input and output nodes are shorted and then the capacitor is connected to discharge the capacitor through a selected memory cell based on whether it is ON or OFF. A programming data latch for each bit line can bias the bit line to either a program enable or program inhibit level.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: August 10, 2021
    Assignee: SanDisk Technologies LLC
    Inventor: Hiroki Yabe
  • Patent number: 11087827
    Abstract: An edge memory array mat with access lines that are split in half, and a bank of sense amplifiers formed in a region that separates the access line segment halves extending perpendicular to the access line segments. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes digit line (DL) jumpers or another structure configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yuan He
  • Patent number: 11081163
    Abstract: According to one embodiment, an information processing apparatus includes a connector into which a first-type semiconductor storage device operating with n types of power supply voltages or a second-type semiconductor storage device operating with m types of power supply voltages less than the n types of power supply voltages is capable of being placed. The apparatus checks whether or not a notch is formed at a predetermined position of a semiconductor storage device placed into the connector, and supplies the m types of power supply voltages to the semiconductor storage device when the notch is formed at the predetermined position.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: August 3, 2021
    Assignee: Kioxia Corporation
    Inventors: Akihisa Fujimoto, Atsushi Kondo
  • Patent number: 11075174
    Abstract: A semiconductor device capable of suppressing generation of noise caused by EMI is provided. The flash memory includes a memory cell array, a clock generator (200), a readout part, an input/output circuit, an overlap detecting part (330) and a clock control part. The clock generator generates an internal clock signal. The readout part reads data from a selected memory cell of the memory cell array using the internal clock signal. The input/output circuit outputs the read data using an external clock signal supplied from outside. The overlap detecting unit detects a period during which a rising edge of the internal clock signal overlaps a rising edge of external clock signal. The clock control part controls a timing of the internal clock signal in response to the detected overlap period.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: July 27, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Takamichi Kasai
  • Patent number: 11074977
    Abstract: A semiconductor device includes a memory block including a plurality of memory strings, each of the plurality of memory strings including one or more dummy transistors, wherein each of the dummy transistors, included in the plurality of memory strings, is programmed to different degrees according to a junction overlap of each of the memory strings.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 27, 2021
    Assignee: SK hynix Inc.
    Inventor: Eun Young Park
  • Patent number: 11069388
    Abstract: A storage device including a nonvolatile memory device including memory blocks and a controller connected with the nonvolatile memory device through data input and output lines and a data strobe line may be provided. The nonvolatile memory device and the controller may be configured to perform training on the data input and output lines by adjusting a delay of a data strobe signal sent through the data strobe line and adjust delays of the data input and output lines based on the training result.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soong-Man Shin, Hyungjin Kim, YoungWook Kim
  • Patent number: 11069392
    Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: July 20, 2021
    Assignee: Rambus, Inc.
    Inventors: Frederick A. Ware, John Eric Linstadt, Brent Steven Haukness, Kenneth L. Wright, Thomas Vogelsang
  • Patent number: 11062754
    Abstract: Apparatuses for executing interrupt refresh are described. An example apparatus includes: memory banks, a sampling timing generator circuit, bank sampling circuits and a command state signal generator circuit that provides a command state signal responsive to a command. Each memory bank includes a latch that stores an address for interrupt refresh. The sampling timing generator circuit receives an oscillation signal and provides a trigger signal of sampling the address. Each bank sampling circuit is associated with a corresponding memory bank. Each bank sampling circuit provides a sampling signal to the latch in the corresponding memory bank responsive to the trigger signal of sampling the address. The sampling timing generator circuit provides the trigger signal of sampling the address, responsive, at least in part, to the command state signal, and the latch stores the address, responsive, at least in part, to the at least one trigger signal of sampling the address.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yutaka Ito, Yuan He
  • Patent number: 11056201
    Abstract: Memory might include a plurality of strings of memory cells, a plurality of access lines each connected to the strings of memory cells, and a controller configured to cause the memory to increase a voltage level applied to each of the access lines, determine a particular voltage level at which each memory cell of a first set of strings of memory cells is deemed to be activated while increasing the voltage level applied to the access lines, decrease the voltage level applied to a particular access line without decreasing the voltage level applied to each remaining access line, and, for each memory cell connected to the particular access line and contained in a second set of strings of memory cells, determine whether that memory cell is deemed to be activated while applying the particular voltage level to the particular access line.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Ramin Ghodsi
  • Patent number: 11037622
    Abstract: A semiconductor device whose operating speed is increased is provided. The semiconductor device includes a write word line, a read word line, a write bit line, a read bit line, a first wiring, and a memory cell. The memory cell includes three transistors of a single conductivity type and a capacitor. Gates of the three transistors are electrically connected to the write word line, a first terminal of the capacitor, and the read word line, respectively. A second terminal of the capacitor is electrically connected to the read bit line. A source and a drain of one transistor are electrically connected to the write bit line and the gate of another transistor, respectively. Two of the three transistors are electrically connected in series between the read bit line and the first wiring. A channel formation region of each of the three transistors includes, for example, a metal oxide layer.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: June 15, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Kiyoshi Kato, Shuhei Maeda
  • Patent number: 11037628
    Abstract: A nonvolatile memory device includes multi-level cells in a memory cell array including a plurality of memory blocks, and each of the memory blocks includes a plurality of pages. A method of operating the nonvolatile memory device includes pre-programming multi-bit data in a pre-program block of the memory blocks, dividing the multi-level cells into a plurality of state groups based on state codes indicating states of the multi-level cells to generate digest data indicating state group codes corresponding to the state groups, and programming the digest data in a digest block of the memory blocks.
    Type: Grant
    Filed: August 17, 2019
    Date of Patent: June 15, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shin-Ho Oh, Min-Cheol Kwon, Sang-Kwon Moon, Sang-Won Jung
  • Patent number: 11031054
    Abstract: Apparatuses and methods for pre-emphasis control are described. An example apparatus includes a pull-up circuit and a pull-down circuit. The pull-up circuit is configured to receive a pull-up data activation signal and drive a data terminal to a pull-up voltage responsive to an active pull-up data activation signal. The pull-down circuit is configured to receive a pull-down activation signal and drive a data terminal to a pull-down voltage responsive to an active pull-down data activation signal. The example apparatus further includes a pull-up pre-emphasis circuit that includes a pre-emphasis timing control circuit configured to provide a timing control signal, and further includes a pull-up logic circuit. A pull-up pre-emphasis control signal based on pull-up data activation signal is provided to control providing pull-up pre-emphasis for greater than one unit interval of data when the pull-up data activation signal remains active for greater than one unit interval.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Junki Taniguchi
  • Patent number: 11031080
    Abstract: A search pattern is generated based on an input search word comprising a first sequence of bits. The search pattern comprises a first set of signals representing the input search word and a second set of signals representing a second sequence of bits comprising an inverse of the first sequence of bits. The search pattern is provided as input to search lines of a content addressable memory (CAM) block. The search pattern causes at least one string in the CAM block to be conductive and provide a signal to a page buffer connected to the string in response to the input search word matching a data entry stored on the string. A location of the data entry is determined based on data read from the page buffer and the location is output.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tomoko Ogura Iwasaki, Manik Advani
  • Patent number: 11024385
    Abstract: A semiconductor device is disclosed including an integrated memory module. The integrated memory module includes a first semiconductor die comprising first non-volatile memory cells, a second semiconductor die comprising second non-volatile memory cells, and a third semiconductor die comprising control circuitry. The first, the second and the third semiconductor die are bonded together. The control circuitry is configured to control memory operations in the first memory cells in parallel with the second memory cells.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 1, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hardwell Chibvongodze, Masatoshi Nishikawa
  • Patent number: 11017862
    Abstract: A multi-time programming memory cell includes a floating gate transistor, a first capacitor, a second capacitor and a third capacitor. The floating gate transistor has a floating gate. A first terminal of the floating gate transistor is coupled to a source line. A second terminal of the floating gate transistor is coupled to a bit line. A first terminal of the first capacitor is connected with the floating gate. A second terminal of the first capacitor is connected with an erase line. A first terminal of the second capacitor is connected with the floating gate. A second terminal of the second capacitor is connected with a control line. A first terminal of the third capacitor is connected with the floating gate. A second terminal of the third capacitor is connected with an inhibit line.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: May 25, 2021
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Chih-Hsin Chen
  • Patent number: 11011212
    Abstract: Methods, systems, and devices for delay calibration oscillators for a memory device are described. In some examples, a memory device may include a delay chain operable (e.g., for a calibration operation) in a ring oscillator configuration that includes a pulse generator. The pulse generator may be configured to output a pulse signal responsive to a transition of an input signal. By generating a pulse signal in a feedback loop of a ring oscillator, the ring oscillator may support a cycle that does not rely on both a first transition propagation pass (e.g., a rising edge propagation) and a responsive, opposite transition propagation pass (e.g., a falling edge propagation) through the delay chain, which may support a ring oscillator cycle time (e.g., period) that more closely represents aspects of the delay chain that are meant to be calibrated.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Hiroshi Akamatsu