Abstract: A detection is made by a processing device allocated to a memory device test board of a distributed test platform that a memory sub-system has engaged with a memory device test resource of the memory device test board. A test is identified to be performed for a memory device of the memory sub-system. The test includes first instructions to be executed by a memory sub-system controller of the memory sub-system in performance of the test and second instructions to be executed by the processing device in performance of the test. The second instructions are to cause one or more test condition components of the memory device test resource to generate one or more test conditions to be applied to the memory device while the memory sub-system executes the first instructions. Responsive to a transmission of the first instructions to the memory sub-system controller, the second instructions are executed.

Abstract: A method of operating a memory device includes: supplying one or more supply voltages to a memory array; and monitoring the one or more supply voltages, which includes: selecting, from the one or more supply voltages, a selected supply voltage; converting, using an analog-to-digital converter (ADC), an internal reference voltage of the memory device and a scaled version of the selected supply voltage into one or more digital values; generating a calibrated measurement result using the one or more digital values; and determining whether the calibrated measurement result is within a pre-determined range.

Abstract: A method is provided for writing a data word to a resistive memory consisting of 2T2R differential cells each having first and second sets of a resistor (R) and a selection transistor (T). The method includes generating an initial codeword, programming it in 1T1R mode, checking its programming in 1T1R mode, inverting it, programming the inverted initial codeword in 1T1R mode, checking its programming in 1T1R mode, and reading, in 2T2R differential mode, that the read data correspond to said initial data. A device designed to implement this write method and to an electronic system including this device is also provided.

Abstract: Electronic devices and methods for single event effect mitigation are described. The device can include a processor, a memory cell, and an integrated particle sensor. The memory cell can comprise a substrate, a deep well coupled to the substrate, and a ground-coupled well coupled to the deep well. The integrated particle sensor can be coupled between the substrate and the deep well, and the ground-coupled well and the deep well. The integrated particle sensor can be operable to detect an ionizing particle generating the single event effect. The electronic device can be a field-programmable gate array. The method can include detecting an ionizing particle generating a single event effect at a memory cell of the electronic device, switching from the memory cell to a redundant memory cell associated with the memory cell when the single event effect is detected, and reconfiguring the memory cell based on the redundant memory cell.

Abstract: A semiconductor device capable of holding analog data is provided. Two holding circuits, two bootstrap circuits, and one source follower circuit are formed with use of four transistors and two capacitors. A memory node is provided in each of the two holding circuits; a data potential is written to one of the memory nodes and a reference potential is written to the other of the memory nodes. At the time of data reading, the potential of the one memory node is increased in one of the bootstrap circuits, and the potential of the other memory node is increased in the other of the bootstrap circuits. A potential difference between the two memory nodes is output by the source follower circuit. With use of the source follower circuit, the output impedance can be reduced.

Abstract: Examples increase precision for aCAMs by converting an input signal (x) received by a circuit into a first analog voltage signal (V(xMSB)) representing the most significant bits of the input signal (x) and a second analog voltage signal (V(xLSB)) representing the least significant bits of the input signal (x). By dividing the input signal (x) bit-wise into the first analog voltage signal (V(xMSB)) and the second analog voltage signal (V(xLSB)), the circuit can utilize aCAM sub-circuits implementing a combination of Boolean operations to search the input signal (x) against 22*M programmable levels, where “M” represents the number of programmable bits for each aCAM sub-circuit. Thus, using similar circuit hardware, example circuits square the number of programmable levels of conventional aCAMs (which generally only have 2M programmable levels). Accordingly, examples provide new aCAMs that can carry out more complex computations than conventional aCAMs of comparable cost, size, and power consumption.

Abstract: An integrated circuit device having a mechanism to check calibration of memory cells configured to perform operations of multiplication and accumulation. The integrated circuit device programs, in a first mode, threshold voltages of first memory cells in a memory cell array to store weight data, and programs, in a second mode, threshold voltages of second memory cells in the memory cell array to store a first result of applying an operation of multiplication and accumulation to a sample input and the weight data. During a calibration check, the integrated circuit device performs the operation using the first memory cells to obtain a second result, and compares the first result, retrieved from the second memory cells, and the second result to determine whether calibration of output current characteristics of the first memory cells programmed in the first mode is corrupted.

Abstract: In an anti-fuse programming control circuit based on a master-slave charge pump structure, a master charge pump module obtains an external voltage and is connected to a plurality of slave charge pump modules. Each slave charge pump module is connected to an anti-fuse bank. The distance between the layout position of each slave charge pump module and the layout position of the connected anti-fuse bank does not exceed a predetermined distance. Based on a programming voltage output by each slave charge pump module to the connected anti-fuse bank, the feedback network outputs a feedback signal corresponding to the slave charge pump module to the master charge pump module. Based on the feedback signal corresponding to each slave charge pump module, the master charge pump module adjusts a master drive signal provided to the slave charge pump module to stabilize the programming voltage output by the slave charge pump module.

Abstract: A system and method for preserving block experiencing wordline failure in memory devices. An example method includes performing, by a processor, a write operation to program data to a set of memory cells addressable by a first wordline of a plurality of wordlines of a block of a memory device; determining that a program fault occurred during the write operation; determining a number of wordlines referenced by a program fault data structure that are associated with the block; and responsive to determining that the number of wordlines fails to satisfy a threshold criterion, releasing a second wordline of the plurality of wordlines to be available for write operations.

Abstract: A method for efficiently waking up ferroelectric memory is provided. A wafer is formed with a plurality of first signal lines, a plurality of second signal lines, a plurality of third signal lines, and a plurality of ferroelectric memory cells that constitute a ferroelectric memory array. Each of the ferroelectric memory cells is electrically connected to one of the first signal lines, one of the second signal lines and one of the third signal lines. Voltage signals are simultaneously applied to the first signal lines, the second signal lines and the third signal lines to induce occurrence of a wake-up effect in the ferroelectric memory cells.

Abstract: An apparatus is described. The apparatus includes a memory chip having logic circuitry to suspend application of an erasure voltage, wherein, respective responses of the erasure voltage to a decision to suspend the application of the erasure voltage depend on where the erasure voltage is along its waveform.

Abstract: A bit line sense amplifier includes a plurality of semiconductor devices including sensing transistors and selection transistors disposed side by side, and configured to sense a voltage change of a bit line and a complementary bit line, and wiring patterns connected to at least one of the plurality of semiconductor devices. The sensing transistors share a source electrode. The selection transistors may be controlled to be complementarily turned on and off. The wiring patterns include a first wiring pattern electrically connecting gate electrodes of the sensing transistors and drain electrodes of the selection transistors, and a second wiring pattern electrically connecting a gate electrode of a sensing transistor and a drain electrode of another sensing transistor.

Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.

Abstract: Memory devices and methods for operating the same are provided. Generally, the device includes an array of multibit-memory-cells, each operable to store multiple bits in separate locations of a charge-trapping layer, and control-circuitry coupled to the array. The control-circuitry is operable read 1st and 2nd bit values of each cell individually based on generated first and second sensed currents, where the first and second sensed currents correspond to charges trapped in first and second bit locations. The control-circuitry executes an algorithm based on the first and second sensed currents and determines a logic state of the cell. In one embodiment, the control-circuitry averages the sensed currents, and compares this to a reference current to determine the logic state. In another, the 2nd bit value is a complement of the 1st, and the control-circuitry compares the currents to determine the logic state without use of a reference current.

Abstract: A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.

Abstract: An integrated circuit chip includes a first through electrode and a second through electrode formed through the integrated circuit chip, a transmission circuit suitable for selecting one of signals transmitted through the first and second through electrodes, respectively, and transmitting the selected signal to a data line, in response to a selection signal, and a selection signal generation circuit suitable for generating the selection signal by toggling the selection signal, during a test operation.

Abstract: A sensing module, a memory device, and a sensing method are provided to perform a read operation so that the un-programmed/programmed state of a memory cell is identified. The sensing module includes a sensing amplifier and a current sink, and both are electrically connected to the memory cell. The sensing amplifier generates a sensing current and identifies the un-programmed/programmed state of the memory cell accordingly. The current sink receives a reference current being equivalent to the summation of the sensing current and a cell current flowing through the memory cell. The reference current is constant, and the sensing current is changed with the cell current. The cell current is generated based on a high read voltage and a low read voltage applied to the memory cell. The sensing current is higher if the memory cell is un-programmed, and the sensing current is lower if the memory cell is programmed.

Abstract: Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.

Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.

Abstract: A memory device includes at least one memory cell block, a first edge block, a second edge block, multiple first sense amplifiers, and multiple second sense amplifiers. The first edge block is coupled to multiple first word lines, where at least one of the first word lines receives an enabled first word line signal. The second edge block is coupled to multiple second word lines, where at least one of the second word lines receives an enabled second word line signal. The first sense amplifiers are disposed between the first edge block and the memory cell block. The second sense amplifiers are disposed between the second edge block and the memory cell block.