Patents Examined by VanThu T. Nguyen
  • Patent number: 10608838
    Abstract: An information provision apparatus whereby information regarding a malfunction or problem that occurred during the use of a prescribed model of home appliance can be shared with users using the same model of home appliance. A device (20) has the following: a presentation-information reception unit (21) that receives presentation information generated by a server (10) and stores the presentation information in a prescribed storage unit; and a presentation unit (22) that presents the presentation information to the user of the device (20), the presentation information having been read out from the aforementioned storage unit. The presentation information indicates malfunctions or problems that occurred in devices that are the same model as the abovementioned device (20) and were being used by other users.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: March 31, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventor: Kotaro Sakata
  • Patent number: 10607676
    Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a cascode may couple a precharged capacitor with the memory cell to transfer a charge between the precharged capacitor and the memory cell. The cascode may isolate the capacitor from the memory cell based on the charge transferred between the capacitor and the memory cell. A second capacitor (e.g., a parasitic capacitor) may continue to provide an additional amount of charge to the memory cell during the read operation. Such a change in capacitance value during the read operation may provide a large sense window due to a non-linear voltage characteristics associated with the change in capacitance value.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Umberto Di Vincenzo
  • Patent number: 10606515
    Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include: a nonvolatile memory device configured to perform internal operations in response to command/address sequences; and a memory controller configured to provide the command/address sequences to the nonvolatile memory device. The memory controller may include: a firmware section configured to manage read/write characteristic information about the nonvolatile memory device; and a hardware section configured to generate command/address sequences based on the read/write characteristic information.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: March 31, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Yeob Chun
  • Patent number: 10586583
    Abstract: Semiconductor memory devices and methods of operating the same are provided. The method of operation may include the steps of selecting a ferroelectric memory cell for a read operation, coupling a first pulse signal to interrogate the selected ferroelectric memory cell, the selected ferroelectric memory cell outputting a memory signal to a bit-line in response to the first pulse signal, coupling the memory signal to a first input of a sense amplifier via the bit-line, electrically isolating the sense amplifier from the selected ferroelectric memory cell, and enabling the sense amplifier for sensing after the sense amplifier is electrically isolated from the selected ferroelectric memory cell. Other embodiments are also disclosed.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: March 10, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Alan D. DeVilbiss, Jonathan Lachman
  • Patent number: 10573374
    Abstract: A data reading error is reduced. A memory cell array in a storage device includes a write word line, a read word line, a write bit line, a read bit line, a source line, and a gain cell. For example, a read transistor in the gain cell can include a metal oxide in a channel formation region. A cancel circuit is electrically connected to the read bit line. The cancel circuit has a function of supplying, to the read bit line, current for canceling leakage current supplied to the read bit line from the gain cell in a non-selected state. In read operation, a potential change of the read bit line due to leakage current is compensated for by the current from the cancel circuit, so that a data reading error is reduced.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: February 25, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Shuhei Nagatsuka
  • Patent number: 10565151
    Abstract: Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: February 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Hyun Yoo Lee
  • Patent number: 10553266
    Abstract: A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: February 4, 2020
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Hideyuki Yoko
  • Patent number: 10546875
    Abstract: At least one latch of a page buffer of a nonvolatile memory device includes a capacitor that selectively stores a voltage of a sensing node. The capacitor includes at least one first contact having a second height corresponding to a first height of each of cell strings, and at least one second contact to which a ground voltage is supplied. The at least one second contact has a third height corresponding to the first height, disposed adjacent to the at least one first contact, and electrically separated from the at least one first contact.
    Type: Grant
    Filed: June 3, 2018
    Date of Patent: January 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chanho Kim, Pansuk Kwak, Chaehoon Kim, Hongsoo Jeon, Jeunghwan Park, Bongsoon Lim
  • Patent number: 10541023
    Abstract: A data line control circuit has a data line driving circuit and a write-assist data line driving circuit. The data line driving circuit is used to drive differential data lines during a write operation of at least one memory cell. The write-assist data line driving circuit is used to drive at least one write-assist data line during the write operation of the at least one memory cell, wherein the at least one write-assist data line is isolated from the differential data lines, and is driven to have a first voltage transition from a first voltage level to a second voltage level, such that one of the differential data lines has a second voltage transition from a third voltage level to a fourth voltage level that is induced by the first voltage transition via capacitive coupling.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: January 21, 2020
    Assignee: MEDIATEK INC.
    Inventors: Chia-Wei Wang, Yi-Te Chiu, Wen-Pin Hsieh
  • Patent number: 10541031
    Abstract: A program circuit may two-dimensionally program data into cells by applying different selected bit line or channel voltages to different bit lines or channels located in different bit line zones of a block during a program operation. The block may be further separated or divided into word line zones. The program circuit may adjust the different bit line or channel voltages as it programs in different word line zones of the block. In accordance with the two-dimensional programming, the program circuit may perform single-pulse program-only SLC program operations.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: January 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mohan Vamsi Dunga, Piyush Dak, Pitamber Shukla
  • Patent number: 10535673
    Abstract: A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: January 14, 2020
    Assignee: Macronix International Co., Ltd.
    Inventors: Teng-Hao Yeh, Chih-Wei Hu, Hang-Ting Lue
  • Patent number: 10510474
    Abstract: A base element for switching a magnetization state of a nanomagnet includes a heavy-metal strip having a surface. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet has a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable in an absence of an external magnetic field by a flow of electrical charge through the heavy-metal strip. A method for switching a magnetization state of a nanomagnet is also described.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: December 17, 2019
    Assignee: University of Rochester
    Inventors: Mohammad Kazemi, Engin Ipek, Eby G. Friedman
  • Patent number: 10510430
    Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least one super block of the flash memory chips; and allocating a buffer memory space to store a plurality of temporary parities generated when data is written into the at least one first super block.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: December 17, 2019
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hong-Jung Hsu
  • Patent number: 10505333
    Abstract: A quantum memory system includes a chalcogenide optical fiber link, a magnetic field generation unit and a pump laser. The chalcogenide optical fiber link includes a photon receiving end opposite a photon output end and is positioned within a magnetic field of the magnetic field generation unit when the magnetic field generation unit generates the magnetic field. The pump laser is optically coupled to the photon receiving end of the chalcogenide optical fiber link. The chalcogenide optical fiber link includes a core doped with a rare-earth element dopant. The rare-earth element dopant is configured to absorb a storage photon traversing the chalcogenide optical fiber link upon receipt of a first pump pulse output by the pump laser. Further, the rare-earth element dopant is configured to release the storage photon upon receipt of a second pump pulse output by the pump laser.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: December 10, 2019
    Assignee: Corning Incorporated
    Inventors: Bruce Gardiner Aitken, Stuart Gray, Daniel Aloysius Nolan, Ji Wang, Jun Yang
  • Patent number: 10482960
    Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including sensing of a snapback current using a set demarcation voltage for set bit mapped cells and a reset demarcation voltage for reset bit mapped cells before selective writes.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Daniel Chu, Kiran Pangal, Mase Taub, Sandeep Guliani, Raymond Zeng
  • Patent number: 10482962
    Abstract: A ternary content addressable memory (TCAM) device includes a memory cell. The memory cell includes a data storage circuit, a limiter circuit, and a discharge circuit. The data storage circuit includes a first resistor and a second resistor connected in series to divide a voltage corresponding to search data, and configured to store cell data. The limiter circuit is configured to receive the divided voltage through an input terminal and transmit an output voltage through an output terminal based on a level of the divided voltage. The discharge circuit discharges a matching line indicating whether the stored cell data matches with the search data, based on the output voltage of the limiter circuit.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 19, 2019
    Assignees: SAMSUNG ELECTRONICS CO., LTD., Research & Business Foundation, Sungkyunkwan Univ.
    Inventors: Cheol Kim, Hyun-Suk Kang, Kee-Won Kwon, Rak-Joo Sung, Sung-Gi Ahn
  • Patent number: 10475503
    Abstract: A circuit for selecting a row of memory cells of a memory device to be refreshed may include: a cold table suitable for storing as a cold row a row selected as a hammered row when the row selected as the hammered row is neither one of cold rows stored in the cold table nor one of hot rows stored in a hot table; and the hot table suitable for storing, as a hot row, the row selected as the hammered row when the row selected as the hammered row is one of the cold rows stored in the cold table.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: November 12, 2019
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Sung-Joo Yoo, Mun-Gyu Son
  • Patent number: 10475513
    Abstract: A resistive memory and a resistance window recovery method for a resistive memory cell thereof are provided. During a first period, an over reset voltage difference is applied between a top electrode and a bottom electrode of the resistive memory cell, wherein the over reset voltage difference falls in a reset complementary switching (reset-CS) voltage range of the resistive memory cell. During a second period, a set voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell to increase a compliance current of the resistive memory cell. During a third period, a reset operation is performed on the resistive memory cell.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: November 12, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Ping-Kun Wang, Shao-Ching Liao, Ming-Che Lin, Min-Chih Wei, Chuan-Sheng Chou
  • Patent number: 10460785
    Abstract: A magnetoresistive random access memory (MRAM) and associated apparatus and methods are described. The MRAM generally includes a heavy metal layer coupled to a source line, and a plurality of bit cells coupled to a word line, a plurality of bit lines, and the heavy metal layer, such that the heavy metal layer is a continuous layer coupling the bit cells to the source line, wherein each of the bit cells comprises a magnetic tunnel junction (MTJ) and a transistor, a gate of the transistor being coupled to the word line, and at least one of a source or a drain of the transistor being coupled to the MTJ or at least one of the bit lines.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Hochul Lee, Chando Park, Seung Hyuk Kang
  • Patent number: 10447267
    Abstract: Systems, methods, and devices are provided for increasing uniformity of wear in semiconductor devices due to, for example, negative-bias temperature instability (NBTI). The method may include receiving a first NBTI control signal. The method may involve receiving a second NBTI control signal based at least in part on the first NBTI control signal. The method may also involve asserting the first NBTI control signal at a clock input pin of a latch. Further, the method may include asserting the second NBTI control signal at a data input pin of the latch. The method may additionally involve toggling electrical elements downstream of the latch based at least in part on an output of the latch based on the first and second NBTI control signals to increase uniformity of wear on the electrical elements in a default low-power state during NBTI toggling mode.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: William C. Waldrop