Patents Examined by VanThu T. Nguyen
  • Patent number: 11195578
    Abstract: One embodiment of a memory device comprises a selector and a storage capacitor in series with the selector. A further embodiment comprises a conductive bridging RAM (CBRAM) in parallel with a storage capacitor coupled between the selector and zero volts. A plurality of memory devices form a 1S-1C or a 1S-1C-CBRAM cross-point DRAM array with 4F2 or less density.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Brian S. Doyle, Elijah V. Karpov, Prashant Majhi
  • Patent number: 11183250
    Abstract: Provided are a memory controller and memory system having an improved threshold voltage distribution characteristic and an operating method of the memory system. As a write request of data with respect to a first block is received, an erase program interval (EPI) is determined denoting a time period elapsed after erasure of the first block. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operation condition selected from among a plurality of operation conditions. when the When the determined EPI is greater than the reference time, the data is programmed to the first block based on a second operation condition selected from among the plurality of operation conditions.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: November 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaeduk Yu, Dongkyo Shim
  • Patent number: 11177016
    Abstract: A non-volatile memory device and an erasing operation method thereof are provided. The non-volatile memory device includes a main memory cell region and a control circuit electrically connected to the main memory cell region. The main memory cell region has a plurality of memory cells. The control circuit is configured to perform an erasing operation on the memory cells, wherein the control circuit is configured to: obtain a current threshold voltage of the memory cell to be erased; calculate a difference between the current threshold voltage and an original threshold voltage to obtain a voltage shift value, wherein the original threshold voltage represents the pre-delivery threshold voltage of the memory cells; adjust an erase verify voltage level according to the voltage shift value; and determine whether the erasing operation is completed according to the adjusted erase verify voltage level.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: November 16, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Jui-Wei Wang
  • Patent number: 11170830
    Abstract: Systems and method are provided for a word line driver. A first supply branch is configured to provide a source voltage level for a word line. A second supply branch is configured to provide a boosted voltage for the word line. The word line driver is configured to apply the source voltage level to the word line based on a first selection signal, and the word line driver is configured to apply the boosted voltage to the word line based on a second selection signal, the second selection signal being delayed relative to the first selection signal.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Sanjeev Kumar Jain
  • Patent number: 11170857
    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected in common to gates of the memory cells, and a control circuit configured to execute a read operation on the memory cells by applying a first read voltage to the word line to determine for each of the memory cells whether or not the memory cell has a threshold voltage that is below the first read voltage and a second read voltage to the word line to determine for each of the memory cells whether or not the memory cell has a threshold voltage that is below the second read voltage. The control circuit determines the first read voltage by applying at least first to third voltages to the word line, and determines the second read voltage based on the first read voltage.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: November 9, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Yoshikazu Harada
  • Patent number: 11164615
    Abstract: A magneto-resistance random access memory (MRAM) cell includes a transistor, a wire and a magnetic tunnel junction (MTJ). The MTJ includes a fixed layer of fixed magnetic polarity electrically connected with the transistor, a free layer of variable magnetic polarity electrically connected with the wire and an insulator between the fixed and free layers. First current passed through the wire destabilizes the variable magnetic polarity of the free layer. Second current passed through the transistor in one of two directions during first current passage through the wire directs the variable magnetic polarity of the free layer toward a parallel or anti-parallel condition with respect to the fixed magnetic polarity of the fixed layer. A ceasing of the first current prior to a ceasing of the second current sets the variable magnetic polarity of the free layer in the parallel or anti-parallel condition.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Luqiao Liu, Jonathan Z. Sun, Daniel C. Worledge
  • Patent number: 11139037
    Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell and a second memory cell capable of storing data and coupled in parallel to a bit line; a first word line coupled to the first memory cell; a second word line coupled to the second memory cell and being different from the first word line; and a control circuit. The first memory cell and the second memory cell share a first well region and are opposed to each other, with the first well region interposed. The control circuit is configured, in a first operation, to repeat application of a first voltage to the first word line and the second word line a plurality of times while increasing the first voltage.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: October 5, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Takashi Maeda
  • Patent number: 11133074
    Abstract: Apparatuses and techniques are described for performing an operation which irreversibly prevents access to a set of memory cells. The operation provides a strong erase bias for select gate transistors of NAND strings. The erase bias induces a phenomenon in the select gate transistors which permanently increases their threshold voltages. This prevents access to the memory cells such as for program or read operations. The operation can involve one or more erase-verify iterations. In each erase-verify iteration, an erase bias is applied to the select gate transistors such as by charging up the channels of the NAND strings and holding a control gate voltage of the select gate transistors at a relatively low level, thereby causing a relatively high channel-to-control gate voltage.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: September 28, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Liang Li, Weihao Wang, Xiaohua Liu, David Joaquin Reed
  • Patent number: 11132307
    Abstract: A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device's primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 28, 2021
    Assignee: Rambus Inc.
    Inventor: Frederick A. Ware
  • Patent number: 11127476
    Abstract: According to one embodiment, a memory system includes a first memory and a memory controller. The first memory is nonvolatile and includes a plurality of memory cell transistors, each of which stores data corresponding to a threshold voltage. The memory controller causes the first memory to execute a read operation to acquire data corresponding to the threshold voltage from the plurality of memory cell transistors on the basis of a result of comparison between the threshold voltage and a read voltage. The memory controller selects a first candidate value from among a plurality of candidate values for the read voltage in accordance with a degree of stress that affects the threshold voltage; and causes the first memory to execute the read operation using the first candidate value as the read voltage.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: September 21, 2021
    Assignee: Kioxia Corporation
    Inventors: Kazutaka Takizawa, Yoshihisa Kojima, Sumio Kuroda, Masaaki Niijima
  • Patent number: 11127477
    Abstract: An E-fuse circuit comprising: an E-fuse group, comprising a plurality of E-fuse sections, wherein each one of the E-fuse sections comprises a plurality of E-fuses; a multi-mode latch circuit, configured to receive an input signal to generate a first output signal in a burn in mode, and configured to receive an address to be compared to generate a second output signal in a normal mode; a first logic circuit group, configured to receive a first part of bits of the first output signal to generate a control signal in the burn in mode; and a second logic circuit group, configured to receive the control signal and a second part of bits of the first output signal to generate a selection signal in the burn in mode, to select which one of the E-fuse sections is activated.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: September 21, 2021
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Tse-Hua Yao, Yi-Fan Chen
  • Patent number: 11120850
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array of memory cells. The sensing circuitry includes a primary latch and a secondary latch. The primary latch is coupled to a pair of complementary sense lines and selectively coupled to a pair of adjacent complementary sense lines. The secondary latch is selectively coupled to the primary latch. The primary latch and secondary latch are configured to shift a data value between the pair of adjacent complementary sense lines and the primary latch. The primary latch and secondary latch are configured to shift the data value from the pair of adjacent complementary sense lines without activating a row line.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 11120842
    Abstract: A memory system includes a first substrate including a first signal terminal and a second signal terminal electrically connected to a bus, a first circuit in which a first switching element and a first resistor are connected in series between a first terminal and a second terminal, the first terminal connected to the first signal terminal, a second circuit in which a second switching element and a second resistor are connected in series between a third terminal and a fourth terminal, the third terminal connected to the second signal terminal, a first memory electrically connected to the second terminal, a second memory electrically connected to the fourth terminal, and a controller electrically connected to the bus and configured to control the first and second switching elements.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: September 14, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Fuminori Kimura
  • Patent number: 11120860
    Abstract: Methods of operating a number of memory devices are disclosed. A method may include adjusting a count of a refresh address counter of at least one memory device of a number of memory devices such that the count of the refresh address counter of the at least one memory device is offset from a count of a refresh address counter of at least one other memory device of the number of memory devices. The method may also include receiving, at each of the number of memory devices, a refresh command. Further, the method may include refreshing, at each of the number of memory devices, a row of memory cells indicated by the count of an associated refresh address counter. Related systems and memory modules are also described.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, James S. Rehmeyer
  • Patent number: 11120878
    Abstract: A method for programming a non-volatile memory (NVM) and an integrated circuit is disclosed. In an embodiment an integrated circuit includes a memory plane organized into rows and columns of memory words, each memory word comprising memory cells and each memory cell including a state transistor having a control gate and a floating gate and write circuitry configured to program a selected memory word during a programming phase by applying a first nonzero positive voltage to control gates of the state transistors of the memory cells that do not belong to the selected memory word.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: September 14, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fran├žois Tailliet, Marc Battista
  • Patent number: 11100997
    Abstract: The disclosure relates to a storage device, a controller and a method for operating a controller. The controller described in embodiments of the disclosure may include a word line grouping circuit configured to group a plurality of word lines in a semiconductor memory device into a plurality of word line groups based on program time information on program times of the respective word lines. Also, the controller may include a super page configuration circuit configured to configure a plurality of super pages including some of the word lines, based on word line group information on the word line groups. Embodiments of the disclosure may provide a storage device, a controller and a method for operating a controller, capable of minimizing program performance degradation that may occur due to deviations in program time among word lines.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: August 24, 2021
    Assignee: SK hynix Inc.
    Inventor: Jin-Suk Lee
  • Patent number: 11101798
    Abstract: A random bit cell includes a selection transistor, a first P-type transistor, and a second P-type transistor. The selection transistor has a first terminal coupled to a source line, a second terminal coupled to a common node, and a control terminal coupled to a word line. The first P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a first bit line, and a floating gate. The second P-type transistor has a first terminal coupled to the common node, a second terminal coupled to a second bit line, and a floating gate. During an enroll operation, one of the first P-type transistor and the second P-type transistor is programmed by channel hot electron injection.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: August 24, 2021
    Assignee: eMemory Technology Inc.
    Inventors: Ying-Je Chen, Wein-Town Sun, Wei-Ming Ku
  • Patent number: 11094383
    Abstract: A computer-implemented method, according to one embodiment, includes: detecting that a calibration of a first page group has been triggered, and evaluating a hierarchical page mapping to determine whether the first page group correlates to one or more other page groups in non-volatile memory. In response to determining that the first page group does correlate to one or more other page groups in the non-volatile memory, a determination is made as to whether to promote at least one of the one or more other page groups for calibration. In response to determining to promote at least one of the one or more other page groups for calibration, the first page group and the at least one of the one or more other page groups are calibrated. Moreover, each of the page groups includes one or more pages in non-volatile memory.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Sasa Tomic, Roman A. Pletka, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry, Timothy J. Fisher
  • Patent number: 11087840
    Abstract: A method of operating a resistive memory device to increase a read margin includes applying a write pulse to a memory cell such that the memory cell is programmed to a target resistance state, and applying a post-write pulse to the memory cell to increase a resistance of the memory cell that is in the target resistance state, the post-write pulse being applied as a single pulse having at least n stepped voltage levels, n being an integer equal to or more than 2, and an n-th stepped voltage level of the post-write pulse is set to be lower than a minimum threshold voltage level of the target resistance state that is changed by an (n?1)-th stepped voltage level of the post-write pulse.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang-woo Lee, Han-bin Noh, Kyu-rie Sim
  • Patent number: 11087801
    Abstract: A memory device stores data for a host device. In one approach, a method includes: selecting, by the memory device, a first mode of operation for a host interface that implements a communication protocol for communications between the memory device and the host device. The host interface is configured to implement the communication protocol using a mode selected by the memory device from one of several available modes. In response to selecting the first mode, resources of the memory device are configured to customize the host interface for operation in the first mode.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Gil Golov