Patents Examined by Vernon P Webb
  • Patent number: 10923619
    Abstract: A semiconductor heterostructure for an optoelectronic device is disclosed. The semiconductor heterostructure includes at least one stress control layer within a plurality of semiconductor layers used in the optoelectronic device. Each stress control layer includes stress control regions separated from adjacent stress control regions by a predetermined spacing. The stress control layer induces one of a tensile stress and a compressive stress in an adjacent semiconductor layer.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 16, 2021
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Alexander Dobrinsky, Maxim S. Shatalov
  • Patent number: 10818584
    Abstract: A package substrate including a redistribution structure and a core is provided. The redistribution structure has a first redistribution surface and a bonding pad disposed on the first redistribution surface. The core is disposed on the redistribution structure and has a first core surface facing towards the first redistribution surface of the redistribution structure. The core has a first core pad disposed on the first core surface and directly bonded to the bonding pad, and the first core pad is offset from the bonding pad. A package structure is also provided.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 27, 2020
    Inventor: Dyi-Chung Hu
  • Patent number: 10777675
    Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane, a first SiC region of a first conductivity type, second and third SiC regions of a second conductivity type provided between the first SiC region and the first plane, a fourth SiC region of the first conductivity type provided between the second SiC region and the first plane, a fifth SiC region of the first conductivity type provided between the third SiC region and the first plane, a gate electrode provided between the second SiC region and the third SiC region, a gate insulating layer, a sixth SiC region of the second conductivity type provided between the first SiC region and the second SiC region, and a seventh SiC region of the second conductivity type provided between the first SiC region and the third SiC region.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: September 15, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki Ohashi, Ryosuke Iijima, Hiroshi Kono, Tatsuo Shimizu
  • Patent number: 10741548
    Abstract: A semiconductor device includes a vertical protection device having a thyristor and a lateral trigger element disposed in a substrate. The lateral trigger element is for triggering the vertical protection device.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: August 11, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Vadim Valentinovic Vendt, Joost Willemen, Andre Schmenn, Damian Sojka
  • Patent number: 10737931
    Abstract: A semiconductor structure includes a first device and a second device. The first device includes a plate including a plurality of apertures; a membrane disposed opposite to the plate and including a plurality of corrugations, and a conductive plug extending through the plate and the membrane. The second device includes a substrate and a bond pad disposed over the substrate, wherein the conductive plug is bonded with the bond pad to integrate the first device with the second device, and the plate includes a semiconductive member and a tensile member, and the semiconductive member is disposed within the tensile member.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Hsien Chang, Chun-Ren Cheng, Wei-Cheng Shen, Wen-Chien Chen
  • Patent number: 10741693
    Abstract: A thin film transistor includes a gate electrode, an active layer formed of oxide semiconductor material on a substrate, and a gate insulation layer therebetween. The active layer includes a channel region corresponding to the gate electrode, a source region at one side of the channel region, and a drain region at the other side of the channel region. The source region includes a first upper portion and the drain region includes a second upper portion that includes the oxide semiconductor material and Si.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 11, 2020
    Assignee: LG Display Co., Ltd.
    Inventor: Ju-Heyuck Baeck
  • Patent number: 10741687
    Abstract: A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: August 11, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yaojian Leng, Richard Foote, Steven J. Adler
  • Patent number: 10741688
    Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Patent number: 10714464
    Abstract: Selective transfer of dies including semiconductor devices to a target substrate can be performed employing local laser irradiation. Coining of at least one set of solder material portions can be employed to provide a planar surface-to-surface contact and to facilitate bonding of adjoining pairs of bond structures. Laser irradiation on the solder material portions can be employed to sequentially bond selected pairs of mated bonding structures, while preventing bonding of devices not to be transferred to the target substrate. Additional laser irradiation can be employed to selectively detach bonded devices, while not detaching devices that are not bonded to the target substrate. The transferred devices can be pressed against the target substrate during a second reflow process so that the top surfaces of the transferred devices can be coplanar. Wetting layers of different sizes can be employed to provide a trapezoidal vertical cross-sectional profile for reflowed solder material portions.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: July 14, 2020
    Assignee: GLO AB
    Inventors: Anusha Pokhriyal, Sharon N. Farrens, Timothy Gallagher
  • Patent number: 10707189
    Abstract: A light-emitting device is provided whose color mixing property and light emission efficiency are improved, while white light with high color rendering performance is ensured by means of four kinds of LED elements emitting red, green, blue, and white light respectively.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: July 7, 2020
    Assignees: Citizen Electronics Co., Ltd., Citizen Watch Co., Ltd.
    Inventors: Masahiko Hamada, Hirohiko Ishii
  • Patent number: 10707188
    Abstract: There is presented a light emitting device, having plural light emitting elements disposed on a substrate, in which a protection element, such as a zener diode, can be disposed at an appropriate position. The light emitting device includes: a substrate; a light emitting section having plural light emitting elements disposed in a mounting area on the substrate; a positive electrode and negative electrode each having a pad section and wiring section to apply voltage to the light emitting section through the wiring sections; a protection element disposed at one of the positive electrode and negative electrode and electrically connected with the other one electrode; and a light reflecting resin formed on the substrate such as to cover at least the wiring sections and the protection element, wherein the wiring sections are formed along the periphery of the mounting area such that one end portions thereof are adjacent to each other.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: July 7, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Haruaki Sasano
  • Patent number: 10622528
    Abstract: A light-emitting device includes: a resin package including: a lead part including a first lead and a second lead, each including a main body portion and a raised portion connected to the main body portion, wherein an upper surface of each of the first lead and the second lead includes a first primary surface portion in the main body portion and a curved portion in the raised portion in a cross-sectional view taken in a direction perpendicular to an upper surface of the lead part, and wherein the curved portion is continuous with and curved upward from an end portion of the first primary surface portion, a resin portion, and a recess defined by a portion of the upper surface of the lead part and the resin portion; and a light-emitting element mounted in the resin package. The curved portion is buried in the resin portion.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 14, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Hironao Oku, Toshiyuki Hashimoto, Mitsuhiro Isono, Takao Ishihara, Takaaki Kato
  • Patent number: 10553820
    Abstract: An encapsulation method and encapsulation structure of an organic light emitting diode (OLED) are provided. The method includes: preparing an OLED substrate, the OLED substrate comprises a base substrate and at least one OLED device formed on the base substrate; forming a first encapsulation layer at a side of the OLED substrate formed with the OLED device to cover the OLED device; and forming a second encapsulation layer on the first encapsulation layer, the second encapsulation layer is a metal layer.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: February 4, 2020
    Assignees: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventors: Yajun Li, Jun Zhang
  • Patent number: 10553692
    Abstract: A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: February 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong-Soo Kim, Sung-Won Lim, Eun-Jeong Kim, Hyun-Jin Chang, Keun Heo, Jee-Hyun Kim
  • Patent number: 10506345
    Abstract: According to an embodiment, a microfabricated structure includes a cavity disposed in a substrate, a first clamping layer overlying the substrate, a deflectable membrane overlying the first clamping layer, and a second clamping layer overlying the deflectable membrane. A portion of the second clamping layer overlaps the cavity.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: December 10, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Wolfgang Klein, Reinhard Gabl
  • Patent number: 10460943
    Abstract: Some embodiments include an integrated structure having a gallium-containing material between a charge-storage region and a semiconductor-containing channel region. Some embodiments include an integrated structure having a charge-storage region under a conductive gate, a tunneling region under the charge-storage region, and a semiconductor-containing channel region under the tunneling region. The tunneling region includes at least one dielectric material directly adjacent a gallium-containing material. Some embodiments include an integrated structure having a charge-trapping region under a conductive gate, a first oxide under the charge-storage region, a gallium-containing material under the first oxide, a second oxide under the gallium-containing material, and a semiconductor-containing channel region under the second oxide.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: October 29, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Chris M. Carlson
  • Patent number: 10388863
    Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: August 20, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 10381585
    Abstract: A thin film transistor includes a gate electrode, a insulating medium layer and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating medium layer. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode, the second end is located on the surface of the insulating medium layer. The semiconducting structure includes a carbon nanotube structure. The second electrode is located on the second end.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 13, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Xiao-Yang Xiao, Ying-Cheng Wang, Yuan-Hao Jin, Tian-Fu Zhang, Qun-Qing Li
  • Patent number: 10374180
    Abstract: A thin film transistor includes a gate, an insulating medium layer and a Schottky diode. The Schottky diode includes a first electrode, a second electrode and a semiconducting structure. The first electrode is located on the surface of the insulating medium layer and includes a first metal layer and a second metal layer. The second electrode is located on the surface of the insulating medium layer and includes a third metal layer and a fourth metal layer. The semiconductor structure includes a first end and a second end. The first end is sandwiched by the first metal layer and the second metal layer, the second end is sandwiched by the third metal layer and the fourth metal layer. The semiconductor structure includes a carbon nanotube structure.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 6, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Xiao-Yang Xiao, Ying-Cheng Wang, Yuan-Hao Jin, Tian-Fu Zhang, Qun-Qing Li
  • Patent number: 10361132
    Abstract: The disclosure relates to semiconductor structures and, more particularly, to structures with thinned dielectric material and methods of manufacture. The method includes depositing a high-k dielectric on a substrate. The method further includes depositing a titanium nitride film directly on the high-k while simultaneously etching the high-k dielectric.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: July 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruqiang Bao, Takashi Ando, Aritra Dasgupta, Kai Zhao, Unoh Kwon, Siddarth A. Krishnan