Patents Examined by Vicki B Booker
  • Patent number: 11005073
    Abstract: An OLED display panel and a manufacturing method of the OLED display panel are provided. A light-transmissive hole is in the OLED display panel, a blocking wall is arranged outside some sub-pixel regions around the light-transmissive hole, and a thin-film encapsulation layer is on the blocking wall. A portion of light emitted from the sub-pixel regions inside the blocking wall is reflected at an interface of the thin film encapsulation layer by total internal reflection to cause a bright light spot, so that an image can also be displayed in the light-transmissive hole. Therefore, an opening for an under-screen camera less affects aesthetics and appearance integrity of the OLED display panel.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: May 11, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Kun Wang
  • Patent number: 10998383
    Abstract: The disclosure discloses a display panel. The display panel includes an optical assembly, a blue-light OLED light source assembly, a red-light OLED light source assembly and a green-light OLED light source assembly, and the optical assembly includes a beam splitting prism. The blue-light OLED light source assembly, the red-light OLED light source assembly and the green-light OLED light source assembly are arranged at three sides of the beam splitting prism, respectively. And blue light emitted by the blue-light OLED light source assembly, red light emitted by the red-light OLED light source assembly and green light emitted by the green-light OLED light source assembly are emitted through the optical assembly. The disclosure also discloses a display device and a head-mounted display device.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: May 4, 2021
    Assignees: Kunshan New Flat Panel Display Technology Center Co., Ltd., KunShan Go-Visionox Opto-Electronics Co., Ltd.
    Inventors: Xiaolong Yang, Rubo Xing, Liwei Ding
  • Patent number: 10998415
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • Patent number: 10991801
    Abstract: A semiconductor device is provided, including: a semiconductor substrate; a transistor section provided in the semiconductor substrate; and a diode section provided in the semiconductor substrate being adjacent to the transistor section, wherein the diode section includes: a second conductivity-type anode region; a first conductivity-type drift region; a first conductivity-type cathode region; a plurality of dummy trench portions arrayed along a predetermined array direction; a contact portion provided along an extending direction of the plurality of dummy trench portions that is different from the array direction; and a lower-surface side semiconductor region provided directly below a portion of the contact portion at an outer end in the extending direction.
    Type: Grant
    Filed: January 26, 2020
    Date of Patent: April 27, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10985323
    Abstract: A light-emitting device includes a plurality of organic EL elements. Each of the organic EL elements includes a reflection electrode, a hole transport region, an electron-trapping luminescent layer, and a light extraction electrode in this order. The hole transport region has a sheet resistance of 4.0×107 ?/sq. or more at a current of 0.1 nA/pixel, and the total thickness of the hole transport region and the electron-trapping luminescent layer is equivalent to an optical path length enabling emission from the electron-trapping luminescent layer to be enhanced.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: April 20, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Norifumi Kajimoto, Tetsuo Takahashi, Koji Ishizuya, Itaru Takaya, Hirokazu Miyashita, Takayuki Ito, Hiroaki Sano
  • Patent number: 10978429
    Abstract: Embodiments relate to mass-transfer methods useful for fabricating products containing Light Emitting Diode (LED) structures. LED arrays are transferred from a source substrate to a target substrate by beam-assisted release (BAR) of a plurality of LED devices in a high-speed flexible manner. The BAR mass-transfer approach is also able to utilize a Known Good Die (KGD) data file of the source substrate to transfer only functionally good die and avoid rework and yield losses.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: April 13, 2021
    Assignee: Apple Inc.
    Inventor: Francois J. Henley
  • Patent number: 10971607
    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Jeff Hu
  • Patent number: 10964636
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first conductive feature over a substrate. The method also includes forming an insulating layer over the substrate and covering the first conductive feature. The method also includes forming a first opening in the insulating layer to expose the first conductive feature. The method also includes recessing the exposed first conductive feature through the first opening, so as to form a second opening in the first conductive feature and below the first opening. The method also includes filling the first opening and the second opening with a second conductive feature.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Yi Yang, Ming-Han Lee
  • Patent number: 10964749
    Abstract: A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: March 30, 2021
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Kai Fu, Houqiang Fu, Yuji Zhao
  • Patent number: 10957817
    Abstract: A polarization field assisted DUV-LED including a bottom substrate and a n-contact/injection layer formed on the bottom substrate. The n-contact/injection layer includes: a first region for accommodating strain relaxation; a second region for lateral access with a low sheet resistance and higher conductivity compared to the first region to minimize resistive losses and heat generation; and a third region of a graded vertical injection layer with low vertical resistance to minimize heat loss due to vertical resistance. The DUV-LED also includes a p-contact region, and an emitting active region between the n-contact/injection layer and the p-contact region. The injection of electrons and holes into quantum wells proceeds due to tunneling of electrons and holes under the barriers due to less than 2 nm thickness of barriers. This carrier injection lowers the Turn ON voltage of LEDs and reduces heat generation.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 23, 2021
    Assignee: Cornell University
    Inventors: Sm Islam, Vladimir Protasenko, Huili Grace Xing, Debdeep Jena
  • Patent number: 10950801
    Abstract: Provided is an organic light emitting device including a cathode; an anode provided opposite to the cathode; a light emitting layer provided between the cathode and the anode; and an organic material layer provided between the cathode and the light emitting layer, and including Compound (A) including a heteroatom and a cyano group, wherein Compound (A) satisfies Equation 1 and Equation 2: |PElCN|?3debye??Equation 1 wherein: |PElCN| means an absolute value of a dipole moment of Compound (A); ? P EI C ? N ? ? P EI ? > ? Ea EI CN ? ? Ea EI ? Equation ? ? 2 wherein: |PElCN| means an absolute value of a dipole moment of Compound (A); |PEl| means an absolute value of a dipole moment of a compound having the same core as the compound of |PElCN| without including a cyano group; |EaElCN| means an absolute value of electron affinity of Compound (A); and |EaEl| means an absolute value of electron affinity of a compound having the same core as the compound of |EaElC
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: March 16, 2021
    Assignee: LG CHEM, LTD.
    Inventors: Jungoh Huh, Sangbin Lee, Sung Kil Hong
  • Patent number: 10921679
    Abstract: The present disclosure provides a projection device for a 3D printer, the projection device including a light source and a display panel for displaying an image to be printed, the image to be printed including a light transmission region and/or a light shielding region. The projection device is configured such that lights emitted from the light source pass through the light transmission region, and that the lights passing through the light transmission region from the light source are non-polarized lights. The present disclosure also provides a 3D printer.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: February 16, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Wenbo Li
  • Patent number: 10916661
    Abstract: The present invention relates to providing a thin film transistor substrate containing a protective film, which can impart high driving stability. The thin film transistor substrate contains a thin film transistor and a protective film containing a cured product of a siloxane composition which covers the thin film transistor, wherein the thin film transistor has a semiconductor layer made of an oxide semiconductor, and wherein the siloxane composition contains polysiloxane, a fluorine-containing compound, and a solvent.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: February 9, 2021
    Assignee: Merck Patent GmbH
    Inventors: Yukiharu Uraoka, Yasuaki Ishikawa, Naofumi Yoshida, Katsuto Taniguchi, Toshiaki Nonaka
  • Patent number: 10903417
    Abstract: A method of forming a magnetic tunnel junction (MTJ) containing device is provided in which a patterned sacrificial material is present atop a MTJ pillar that is located on a bottom electrode. A passivation material liner and a dielectric material portion laterally surround the MTJ pillar and the patterned sacrificial material. The patterned sacrificial material is removed from above the MTJ pillar and replaced with a top electrode. A seam is present in the top electrode. The method mitigates the possibility of depositing resputtered conductive metal particles on a sidewall of the MTJ pillar. Thus, improved device performance, in terms of a reduction in failure mode, can be obtained.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Alexander Reznicek, Nathan P. Marchack, Bruce B. Doris
  • Patent number: 10896935
    Abstract: The disclosure relates to a display panel, a method for fabricating the same, and a display device. The display panel includes: a base substrate, and a thin film transistor structure, an anode layer, a light-emitting layer, a cathode layer, and an encapsulation layer, which are arranged successively on the base substrate, wherein at least one installation hole for installing a hardware structure is arranged in a display area of the display panel, and the installation hole runs through the base substrate and the respective layers on the display panel in the direction perpendicular to the base substrate; and the edge of the installation hole is arranged with an encapsulation layer material, and the encapsulation layer material covers at least the light-emitting layer and the cathode layer adjacent to the edge of the installation hole, in the direction parallel to the base substrate.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: January 19, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Tao Sun, Song Zhang, Tao Wang
  • Patent number: 10879466
    Abstract: An organic light-emitting display apparatus including: a substrate; a plurality of first electrodes spaced apart from each other on the substrate; a plurality of organic functional layers respectively covering an upper surface and side surfaces of the plurality of first electrodes, each of the plurality of organic functional layers including an emission layer; a first bank disposed between the plurality of organic functional layers and not directly contacting the plurality of first electrodes; and a second electrode disposed on the plurality of organic functional layers.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: December 29, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyunsung Bang, Arong Kim, Jungsun Park, Duckjung Lee
  • Patent number: 10874300
    Abstract: An embodiment of a sensor device includes a base substrate, a circuit pattern formed overlying the interior surface of the substrate, a physiological characteristic sensor element on the exterior surface of the substrate, conductive plug elements located in vias formed through the substrate, each conductive plug element having one end coupled to a sensor electrode, and having another end coupled to the circuit pattern, a multilayer component stack carried on the substrate and connected to the circuit pattern, the stack including features and components to provide processing and wireless communication functionality for sensor data obtained in association with operation of the sensor device, and an enclosure structure coupled to the substrate to enclose the interior surface of the substrate, the circuit pattern, and the stack.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 29, 2020
    Assignee: MEDTRONIC MINIMED, INC.
    Inventors: Daniel Hahn, David Probst, Randal Schulhauser, Mohsen Askarinya, Patrick W. Kinzie, Thomas P. Miltich, Mark D. Breyen, Santhisagar Vaddiraju
  • Patent number: 10879402
    Abstract: A thin film transistor includes a substrate, a semiconductor layer, a first gate insulating film, a second gate insulating film, and a gate electrode. The semiconductor layer is provided in a selective region of the substrate. The first gate insulating film is provided in the selective region of the substrate and covers a surface of the semiconductor layer. The second gate insulating film extends across opposite sides of the first gate insulating film along a channel width direction and covers the first gate insulating film that covers the semiconductor layer. The gate electrode faces the semiconductor layer across the second gate insulating film.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: December 29, 2020
    Assignee: JOLED INC.
    Inventors: Naoki Asano, Tokuaki Kuniyoshi
  • Patent number: 10875957
    Abstract: Four conjugated copolymers with a donor/acceptor architecture including 4,4-dihexadecyl-4H-cyclopenta[1,2-b:5,4-b?]dithiophene as the donor structural unit and benzo[2,1,3]thiodiazole fragments with varying degrees of fluorination have been synthesized and characterized. It has been shown that the HOMO levels were decreased after the fluorine substitution. The field-effect charge carrier mobility was similar for all polymers with less than an order of magnitude difference between different acceptor units.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: December 29, 2020
    Assignee: The Regents of the University of California
    Inventors: Ming Wang, Guillermo C. Bazan
  • Patent number: 10879278
    Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The manufacturing method of the display substrate includes: forming a pattern of first transparent conductive layer, forming a passivation layer and forming a second transparent conductive layer on the passivation layer, forming a pattern of second transparent conductive layer, i.e., a slit electrode, the pattern of second transparent conductive layer including a plurality of sub-electrodes arranged at intervals and located in a display region of the display substrate; and removing a portion of the passivation layer which is in the display region and is not covered by the sub-electrodes, forming a pattern of passivation layer. The second transparent conductive layer is polycrystalline ITO.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: December 29, 2020
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jiaxiang Zhang, Fengtao Wang, Yanqiang Wang