Abstract: An array substrate includes a base and a pixel defining layer and light-emitting layers that are disposed on the base. The pixel defining layer includes defining strips extending in a first direction and defining portions extending in a second direction, the defining strips and the defining portions define openings, defining portions located between two adjacent defining strips are spaced apart in the first direction, a defining portion includes at least two second sub-portions and first sub-portion(s) connected to the two adjacent defining strips through the at least two second sub-portions, thickness of a defining strip is greater than a thickness of a first sub-portion, and the thickness of the first sub-portion is greater than a thickness of a second sub-portion. Portion(s) of a light-emitting layer is disposed in a corresponding opening, and at least two light-emitting layers between the two adjacent defining strips are connected to form a one-piece structure.

Abstract: Extrinsic structures formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. An example integrated device including such an intrinsic structure includes a semiconductor device having an active region in a conduction layer, an isolation region in the conduction layer, an insulating layer formed over at least a portion of the active region and over at least a portion of the isolation region, a via outside the active region, and a conductive interconnect. The isolation region extends around the semiconductor device in an area outside the active region. The via extends through the insulating layer and down to the isolation region in the conduction layer, and the conductive interconnect is formed directly on the isolation region in the conduction layer.

Abstract: A display substrate including: a base substrate with a display region, an encapsulation region and an edge region on a periphery of the encapsulation region, the edge region includes a bonding region on at least one side of the base substrate; a plurality of stacked inorganic film layers on a side of the base substrate; a plurality of first grooves, at the edge region, spaced apart from each other in a direction distal from the encapsulation region, and extending along a periphery of the base substrate, at least one of the plurality of first groove runs through at least one inorganic film layer of the plurality of inorganic film layers, and a distance between each first groove and the display region is larger than that between each first groove and an edge of the base substrate; and an organic layer.

Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a dielectric over a conductive layer, and a conductive line on the dielectric. The package substrate includes a plurality of conductive bumps on a surface of the conductive line, where the conductive bumps are conductively coupled to the conductive line, and a solder resist over the conductive line and the dielectric. The surface of the conductive line may be a bottom surface, where the conductive bumps are below the conductive line and conductively coupled to the bottom surface of the conductive line, and where the conductive bumps may be embedded in the dielectric. The surface of the conductive line may be a top surface, where the conductive bumps are above the conductive line and conductively coupled to the top surface of the conductive line, and wherein the conductive bumps are embedded in the solder resist.

Abstract: A display apparatus is disclosed that includes a first display area and a second display area adjacent to the first display area. The first and second display areas include first and second light emitting areas having first and second pixel densities, respectively. The first and second light emitting areas at an interface between the first and second display areas are arranged such that in operation light emitted by the first and second light emitting areas produces a gradual decrease in light intensity from the first display area to the second display area near the interface.

Abstract: An array substrate, including: a plurality of first pixel defining portions and a plurality of second pixel defining portions arranged on a base substrate and jointly define a plurality of pixel openings; and a light emitting functional layer arranged on the base substrate and includes a first light emitting portion and a second light emitting portion that emit different colors of light, at least a part of the first light emitting portion and the second light emitting portion is respectively located in a first pixel opening and a second pixel opening. An orthographic projection of a combination of two adjacent pixel openings separated by the second pixel defining portion on a base substrate has a first size in a first direction and a second size in a second direction, and a ratio of the first size to the second size is within a range of 0.8 to 1.2.

Abstract: The present disclosure provides a display panel comprising multiple first, second and third sub-pixels having first, second and third effective light-emitting regions respectively. In a row direction, the first effective light-emitting regions form first rows of effective light-emitting regions, and the second and third effective light-emitting regions are alternately arranged to form second rows of effective light-emitting region. The first and second rows are alternately arranged in a column direction perpendicular to the row direction. A virtual quadrilateral is formed by lines connecting geometric centers of gravity of four first effective light-emitting regions in two adjacent rows and two adjacent columns. Geometric centers of gravity of the second and third effective light-emitting region are located in corresponding virtual quadrilaterals respectively.

Abstract: A method includes forming a gate stack, which includes a gate dielectric and a metal gate electrode over the gate dielectric. An inter-layer dielectric is formed on opposite sides of the gate stack. The gate stack and the inter-layer dielectric are planarized. The method further includes forming an inhibitor film on the gate stack, with at least a portion of the inter-layer dielectric exposed, selectively depositing a dielectric hard mask on the inter-layer dielectric, with the inhibitor film preventing the dielectric hard mask from being formed thereon, and etching to remove a portion of the gate stack, with the dielectric hard mask acting as a portion of a corresponding etching mask.

Abstract: The embodiments of the present application provide a package cover plate and a manufacturing method thereof, a display panel and a display device. The package cover plate includes a cover plate structure layer, a spacer structure on a side of the cover plate structure layer, the spacer structure includes a first spacer, and the first spacer includes a water absorbing structure, and an auxiliary electrode layer on a side of the spacer structure facing away from the cover plate structure layer.

Abstract: An array substrate, a manufacturing method thereof, and a display panel are provided. The array substrate includes a bending area and a non-bending area, and further includes an inorganic stacked layer disposed on a substrate layer. A recess is formed on the inorganic stacked layer in the bending area. A plurality of first metal lines are disposed in the inorganic stacked layer at two sides of the bending area. A filling layer is filled in the recess. The array substrate further includes a second metal line disposed on the inorganic stacked layer and the filling layer, and the first metal lines at the two sides of the bending area form a lap joint by the second metal line.

Abstract: Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.

Abstract: An organic light emitting diode (OLED) display device and a method of manufacturing thereof are provided. The organic light emitting diode display device includes a display area and a non-display area. The display area includes a pixel area and a photosensitive area disposed between the pixel areas. The photosensitive area includes a first thin film transistor. The pixel area includes a second thin film transistor, which the same type as the first thin film transistor. The non-display area includes a third thin film transistor, which is a different type from the first thin film transistor.

Abstract: A display device includes: a base layer including a display area (DA) and a non-DA; a circuit element layer on the base layer and including: a power supply electrode (PSE) overlapping the non-DA, circuit elements, and a shielding electrode connected to the PSE and overlapping some of the circuit elements; a display element layer on the circuit element layer and including: a light emitting element including a first electrode, a light emitting unit, and a second electrode, and a connection electrode connecting the second electrode to the PSE and including first through-holes; a thin film encapsulation layer (TFEL) on the display element layer and including an organic layer overlapping the DA; and an input sensing layer on the TFEL and including sensing electrodes and sensing signal lines connected to the sensing electrodes. The sensing signal lines overlap the connection electrode. Some of the first through-holes overlap the shielding electrode.

Abstract: A self-luminous display panel 10 in which self-luminous elements 2 are arranged on a plane, wherein each of the self-luminous elements includes: a pair of electrodes 13, 20 disposed facing each other, an electrode of the pair of electrodes including a metal layer 20A; functional layers 15, 16, 17, 18, 19 including a light emitting layer 17, disposed between the pair of electrodes; and a sealing layer 21 that covers the pair of electrodes and the functional layers from a direction. The self-luminous elements include a repaired self-luminous element 2?. The repaired self-luminous element includes a foreign object FO among the functional layers. The electrode including the metal layer has a high resistance portion 201 surrounding, in plan view, an area containing the foreign object, and has a thickened portion 202 of the metal layer at an outer edge, in plan view, of the high resistance portion.

Abstract: A substrate module includes a first substrate and a transistor unit. The transistor unit is disposed on the first substrate, and the transistor unit includes an active layer, a first electrode, and a second electrode. The active layer has a first surface and a second surface, and the first surface is opposite to the second surface. The first electrode and the second electrode at least partially overlap the active layer. The second surface contacts the first electrode and the second electrode. A first gallium concentration exists within a first range in the active layer, the first range is adjacent to the second surface of the active layer, a second gallium concentration exists within a second range in the active layer, the second range is adjacent to the first surface of the active layer, and the first gallium concentration is higher than the second gallium concentration.

Abstract: An active matrix substrate including a resin substrate including a plurality of external connection terminals arranged near a display region, the active matrix substrate includes: a plurality of first lead wires each extending from one of the external connection terminals to the display region; and a plurality of second lead wires each extending from one of the external connection terminals to a separation line, the second lead wires being arranged with an arrangement pitch along the separation line, and the arrangement pitch of the second lead wires being greater than an arrangement pitch of the first lead wires.

Abstract: A light emitting device including a first electrode, a second electrode, a quantum dot layer disposed between the first electrode and the second electrode and a first auxiliary layer disposed between the quantum dot layer and the first electrode, wherein the first auxiliary layer includes nickel oxide nanoparticles having an average particle diameter of less than or equal to about nanometers (nm) and an organic ligand, a method of manufacturing the light emitting device, and a display device including the same.

Abstract: The present disclosure provides a mask plate, a display panel and a display device. The mask plate comprises: a transparent substrate; an opaque film layer, the opaque film layer being disposed on the transparent substrate. The opaque film layer includes a plurality of first regions and a plurality of second regions, a first sub-region in the first region and the second region are transmissive, and the remaining portion in the first region is semi-transmissive. The mask plate is used to form via holes in the planarization layer of the display panel by exposure, so that the angles between the metal electrode layers disposed in the via holes and the source/drain layers of the display panel are small and diversified, decreasing the visibility of the metal electrode layers.

Abstract: A semiconductor device package includes a first substrate, a second substrate, and a first electronic component between the first substrate and the second substrate. The first electronic component has a first surface facing the first substrate and a second surface facing the second substrate. The semiconductor device package also includes a first electrical contact disposed on the first surface of the first electronic component and electrically connecting the first surface of the first electronic component with the first substrate. The semiconductor device package also includes a second electrical contact disposed on the second surface of the first electronic component and electrically connecting the second surface of the first electronic component with the second substrate. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: A semiconductor structure includes a first FET device, a second FET device disposed, and an isolation separating the first FET device and the second FET device. The first FET device includes a fin structure, a first work function metal layer disposed over the fin structure, and a high-k gate dielectric layer between the first work function metal layer and the fin structure. The second FET device includes a plurality of nanosheets separated from each other, a second work function metal layer surrounding each of the nanosheets, and the high-k gate dielectric layer between the second work function metal layer and each of the nanosheets. A portion of the high-k gate dielectric layer is directly over the isolation.