Patents Examined by Vinh P. Nguyen
  • Patent number: 11650244
    Abstract: A test circuit includes one or more sensors adapted to be formed on a wafer, each sensor detecting one or more wafer characterization data in a stressed condition; a stress generator controlling the one or more sensors to place the one or more sensors under stress during wafer manufacturing; memory coupled to the one or more sensors to store wafer characteristics under the stressed condition; and an interface coupled to the memory to communicate the wafer characterization data to a tester.
    Type: Grant
    Filed: June 5, 2021
    Date of Patent: May 16, 2023
    Inventor: Alan Paul Aronoff
  • Patent number: 11644502
    Abstract: A circuit and a method for reducing interference of power on/off to hardware test. The circuit includes: a power unit, a voltage processing unit, a PSU and a to-be-tested hardware. An input terminal of the voltage processing unit is connected to the power unit, an output terminal of the voltage processing unit is connected to an input terminal of the PSU, and an output terminal of the PSU is connected to the to-be-tested hardware; the power unit is configured to provide an operating voltage; the voltage processing unit is configured to eliminate electric sparks caused by instability of the operating voltage at an instant of power on/off; the PSU is configured to convert a stable operating voltage outputted from the voltage processing unit into a direct current voltage required for the to-be-tested hardware; and the to-be-tested hardware is configured to receive the direct current voltage outputted from the PSU.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 9, 2023
    Assignee: ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY CO., LTD.
    Inventor: Zhihua Ge
  • Patent number: 11644483
    Abstract: A sensor device for detecting voltage in a conductor cable includes a sense electrode to be disposed over a surface of the conductor cable to cover a sense region having a sense axial width and a sense circumferential length and a reference electrode to be disposed over the surface of the conductor cable to cover a reference region. The reference region has an axial position adjacent the axial position of the sense region and has a reference circumferential length greater than the sense circumferential length. The sensor device further includes a charge measurement circuit connected in series between the sense electrode and the reference electrode to measure a charge measurement and circuitry to compare the charge measurement to a threshold to detect a presence of the voltage in the conductor cable.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: May 9, 2023
    Assignee: RF Code, Inc.
    Inventors: Jonathan Andrew Guy, Jacob Aaron Perlmutter, Iurii Buiankin
  • Patent number: 11639957
    Abstract: One example includes a cryogenic wafer test system. The system includes a first chamber that is cooled to a cryogenic temperature and a wafer chuck confined within the first chamber. The wafer chuck can be configured to accommodate a wafer device-under-test (DUT) comprising a plurality of superconducting die. The system also includes a second chamber that is held at a non-cryogenic temperature and which comprises a wafer chuck actuator system configured to provide at least one of translational and rotational motion of the wafer chuck via mechanical linkage interconnecting the wafer chuck and the wafer chuck actuator system. The system further includes a radiation barrier arranged between the first chamber and the second chamber and through which the mechanical linkage extends, the radiation barrier being configured to provide a thermal gradient between the cryogenic temperature of the first chamber and the non-cryogenic temperature of the second chamber.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: May 2, 2023
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Kelsey McCusker, Stanley Katsuyoshi Wakamiya, Jonathan Shane Atienza, Jonathan Francis Van Dyke, Kevin Collao
  • Patent number: 11630153
    Abstract: A chip testing apparatus and system suitable for performing testing on multiple chips in a chip cluster are provided. The chip testing apparatus includes a signal interface and a test design circuit. The signal interface transmits an input signal and multiple driving signals in parallel from a test equipment to each of the chips. The test design circuit receives multiple output signals from the chips through the signal interface and serially outputs a test data to the test equipment according to the output signals.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: April 18, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Chih-Chiang Lai, Cheng-Ching Huang
  • Patent number: 11624771
    Abstract: The present disclosure provides an apparatus for illumination inspection of micro LEDs. An apparatus for illumination inspection of micro LEDs includes a surface-contact probe making a surface contact, through an electrical resistive material, with a front surface of an LED assembly of multiple micro LEDs arranged forwardly and interconnecting LED electrodes at both ends of the micro LEDs, probe electrodes to be in line contact with one side and the other side of the surface-contact probe for supplying electric power, an imaging unit for photographing the LED assembly from an opposite surface of the surface-contact probe, to where the surface-contact probe is contacted, and a control unit for supplying electric power to the probe electrodes forwardly along the micro LEDs as aligned and for inspecting the micro LEDs illumination based on images of the LED assembly photographed by the imaging unit before and after supplying the electric power.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: April 11, 2023
    Assignee: Microinspection, Inc.
    Inventors: Tak Eun, Ho Hack Kim, Beom Jin Kim, Dong Jun Lee
  • Patent number: 11619660
    Abstract: Methods and systems are disclosed for sensing an environment electric field. In one exemplary implementation, a method includes disposing a sensor in the environment, wherein the sensor comprising a crystalline lattice and at least one optically-active defect in the crystalline lattice; pre-exciting the crystalline lattice to prepare at least one defect in a first charge state using a first optical beam at a first optical wavelength; converting at least one defect from the first charge state to a second charge state using a second optical beam at a second optical wavelength; monitoring a characteristics of photoluminescence emitted from the defect during or after the conversion of the at least one defect from the first charge state to the second charge state; and determining a characteristics of the electric field in the environment according to the monitored characteristics of the photoluminescence.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: April 4, 2023
    Assignee: The University of Chicago
    Inventors: Gary Wolfowicz, Samuel James Whiteley, David Daniel Awschalom
  • Patent number: 11614350
    Abstract: A sensor test apparatus having excellent versatility is provided. The sensor test apparatus includes a first application unit 40 including a first application device including a socket to which the sensor is electrically connected, and a pressure chamber 43 which applies pressure to the sensor, a test unit which tests the sensor 90 via the socket, a conveying robot which conveys the sensor into and out of the first application unit 40, and an apparatus main body which houses the first application unit 40, the test unit 35 and the conveying robot, and the apparatus main body has an opening which allows the first application unit 40 to be inserted into the apparatus main body and removed from the apparatus main body to an outside.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: March 28, 2023
    Assignee: ADVANTEST Corporation
    Inventors: Kazunari Suga, Daisuke Takano, Satoshi Hanamura, Michiro Chiba, Hisao Nishizaki, Atsushi Hayakawa
  • Patent number: 11614469
    Abstract: A non-contact electric potential meter system to determine voltage between an AC conductor and a reference potential without direct electrical contact to the conductor. A housing provides a shielded measurement region that excludes other conductors and holds power supply means; an AC voltage sensing mechanism includes a conductive sense plate and an electrical connection to the reference potential. Waveform-sensing electronic circuitry obtains an AC voltage waveform induced by capacitive coupling between the conductor and the conductive sense plate. Capacitance-determining electronic circuitry obtains a scaling factor based on the coupling capacitance formed between the conductor and the conductive sense plate. Signal processing electronic circuitry uses the AC voltage waveform and the coupling capacitance-based scaling factor to obtain the voltage between the conductor and the reference potential.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: March 28, 2023
    Assignee: Interbay Assets, LLC
    Inventors: Prabal Dutta, Michael C. Lorek, Brian Andika Purnomo, Aaron Block
  • Patent number: 11609262
    Abstract: An integrated circuit die includes a core fabric configurable to include an aging measurement circuit and a device manager coupled to the core fabric to operate the aging measurement circuit for a select period of time. The aging measurement circuit includes a counter to count transitions of a signal propagating through the aging measurement circuit during the select period of time when the aging measurement circuit is operating. The transitions of the signal counted by the counter during the select period of time are a measure of an aging characteristic of the integrated circuit die.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: March 21, 2023
    Assignee: Intel Corporation
    Inventors: Dheeraj Subbareddy, Ankireddy Nalamalpu, Mahesh A. Iyer, Dhananjay Raghavan
  • Patent number: 11609264
    Abstract: There is provided an attenuation amount setting unit that sets, in a case where signals are simultaneously output from all output ports of a plurality of interface units at the same signal level, one of the plurality of interface units as the reference interface unit, and adds a difference between an attenuation amount of a second attenuator stored in a storage unit of the reference interface unit and an attenuation amount of another second attenuator stored in another storage unit of the other interface unit to an attenuation amount of each of a plurality of third attenuators of the other interface unit to correct the attenuation amount.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: March 21, 2023
    Assignee: ANRITSU CORPORATION
    Inventors: Koichiro Tomisaki, Jesse Paulo Valencia Macabasco
  • Patent number: 11609203
    Abstract: The disclosure describes techniques for detecting a crack or defect in a material. The technique may include applying an electrical signal to a first electrode pair electrically coupled to the material. The technique also may include, while applying the electrical signal to the first electrode pair, determining a measured voltage between a second, different electrode pair. At least one electrode of the second, different electrode pair is electrically coupled to the material. The technique may further include determining a corrected measured voltage by suppressing a thermally induced voltage from the measured voltage and determining whether the material includes a crack or other defect based on the corrected measured voltage.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: March 21, 2023
    Assignee: 3M Innovative Properties Company
    Inventors: David H. Redinger, Christopher R. Yungers, Jennifer F. Schumacher
  • Patent number: 11598820
    Abstract: A load testing device includes: a resistance unit; a cooling fan that cools the resistance unit; a circuit breaker; a first terminal part that is connected to a test target power source; and a charge/discharge unit that has a charger and a first power storage device. The charge/discharge unit is connected with a test target power source cable being between the first terminal part and the resistance unit, between the first terminal part and the circuit breaker. The first power storage device 45a stores electric power supplied from the test target power source. The cooling fan drives based on electric power from at least the charge/discharge unit.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 7, 2023
    Assignee: TATSUMI RYOKI CO., LTD
    Inventor: Toyoshi Kondo
  • Patent number: 11598815
    Abstract: This application relates to a battery test system and a battery test method. The battery test system according to an embodiment comprises: an extrusion apparatus configured to be disposed on a first surface of a battery; and a pressure apparatus, disposed above the extrusion apparatus, where the pressure apparatus is configured to apply a predetermined force to the battery in predetermined duration through the extrusion apparatus. The battery test system and the battery test method provided in this application are able to more reasonably evaluate the safety of the soft package battery and identify the risk caused by the defect of the soft package battery.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: March 7, 2023
    Assignee: NINGDE AMPEREX TECHNOLOGY LIMITED
    Inventors: Xiaoqing Yu, Shi Tan, Zhu Feng, Zhiwen Xiao
  • Patent number: 11600539
    Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: March 7, 2023
    Inventors: Min-Jae Lee, Sang-Lok Kim, Byung-Hoon Jeong, Tae-Sung Lee, Jeong-Don Ihm, Jae-Yong Jeong, Young-Don Choi
  • Patent number: 11592497
    Abstract: A method for monitoring one or more characteristics of an ultracapacitor is provided. The method includes obtaining a plurality of voltage measurements. Each of the voltage measurements can be obtained sequentially at one of a plurality of intervals. Furthermore, each of the voltage measurements can be indicative of a voltage across the ultracapacitor. The method can include determining an actual voltage step of the ultracapacitor based on two consecutive voltage measurements of the plurality of voltage measurements. The method can further include determining whether the actual voltage step exceeds a threshold voltage step of the ultracapacitor. Furthermore, in response to determining the actual voltage step exceeds the threshold voltage, the method can include providing a notification associated with performing a maintenance action on the ultracapacitor.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: February 28, 2023
    Assignee: KYOCERA AVX COMPONENTS CORPORATION
    Inventor: Joseph M. Hock
  • Patent number: 11592472
    Abstract: An apparatus for testing integrated circuits (ICs) , includes a first thermal contact structure having a first surface to interface with a heat source and an opposing second surface to interface with a device under test (DUT). A second thermal contact structure is above the first thermal contact structure and separated therefrom by a variable-resistance thermal interface (VRTI) structure operable to couple or decouple the first and second thermal contact structures from one another. The VRTI structure has a maximal thermal conductivity associated with a first state, and a minimal thermal conductivity associated with a second state.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: February 28, 2023
    Assignee: Intel Corporation
    Inventors: Joe F. Walczyk, James Hastings, Morten Jensen, Todd Coons
  • Patent number: 11579007
    Abstract: A method for calibrating a device for measuring a mass of fuel carried by an aircraft by: receiving a message containing a reference permittivity, a reference density and a reference volume, determining a first calibration coefficient as a function of the reference permittivity, determining a second calibration coefficient as a function of the reference volume, determining a third coefficient of calibration as a function of the reference density, determining a calibrated mass of fuel as a function of a determined height of fuel corrected as a function of the first calibration coefficient, a volume of fuel determined as a function of the corrected height and corrected as a function of the second calibration coefficient, and a mass of fuel determined as a function of the corrected volume and corrected as a function of the third calibration coefficient.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: February 14, 2023
    Assignee: Airbus Operations SAS
    Inventors: Emre Kanyilmaz, Alvaro Ruiz Gallardo
  • Patent number: 11577623
    Abstract: The present invention relates to a system for predicting battery usage habits and battery discharge tendencies. The system includes a battery sensor that senses a state of charge (SOC) of a battery and a controller hat calculates battery power generation amount during driving time of a vehicle and battery consumption during parking time of the vehicle based on information sensed by the battery sensor. A storage unit for stores the battery power generation amount, the battery consumption, time at which the vehicle is tuned on/off, and time at which the controller enters a sleep/wake-up state.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: February 14, 2023
    Assignees: Hyundai Motor Company, Kia Motors Corporation, Yura Corporation Co., Ltd.
    Inventors: Hyun Wook Kim, Hyun Young Kim, Chan Young Jung
  • Patent number: 11579171
    Abstract: Probe cards for probing highly-scaled integrated circuits are provided. A probe card includes a backplane and an array of probes extending from the backplane. Each of the probes includes a cantilever member and a probe tip. A first end of the cantilever member is coupled to the backplane, such that the cantilever member extends from the backplane. The probe tip extends from a second end of the cantilever member. The probes are fabricated from semiconductor materials. Each probe is configured to transmit electrical signals between the backplane and a device under test (DUT), via corresponding electrodes of the DUT. The probes are highly-scaled such that the feature size and pitch of the probes matches the highly-scaled feature size and pitch of the DUT's electrodes. The probes comprise atomic force microscopy (AFM) probes that are enhanced for increased electrical conductivity, elasticity, lifetime, and reliability.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: February 14, 2023
    Assignee: Meta Platforms Technologies, LLC
    Inventor: Christopher Percival