Patents Examined by Vongsavanh Sengdara
  • Patent number: 11565933
    Abstract: A sensor device may include a base layer, and an ASIC element disposed on the base layer. The ASIC element may include a plurality of electrical contact points. The sensor device may include a MEMS element. The MEMS element may include a plurality of through-silicon vias. The sensor device may include a plurality of conductive contact elements. Each conductive contact element may be disposed between, and electrically coupling, a respective through-silicon via and a respective electrical contact point. The sensor device may include a protective layer disposed between the ASIC element and the MEMS element. The protective layer may be composed of material(s) having a physical property defined to permit the protective layer to mitigate stress forces directed from the ASIC element to the MEMS element, to prevent corrosion, and/or to prevent leakage current between electrical connections due to pollution and/or humidity.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: January 31, 2023
    Assignee: Infineon Technologies AG
    Inventors: Michael Kandler, Alfred Niklas
  • Patent number: 11569456
    Abstract: An organic electroluminescence device includes: an anode; an emitting layer; and a cathode, the emitting layer containing a first material, a second material and a third material, the first material being a fluorescent material, the second material being a delayed fluorescent material, the third material having a singlet energy larger than a singlet energy of the second material.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: January 31, 2023
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Toshinari Ogiwara, Kei Yoshida, Ryohei Hashimoto, Yumiko Mizuki
  • Patent number: 11557640
    Abstract: A circuit board includes a board, first connection pads disposed on the board and arranged in a first direction, second connection pads disposed on the board and arranged in the first direction, the second connection pads spaced apart from the first connection pads in a second direction perpendicular to the first direction, and a driving chip disposed on the board between the first connection pads and the second connection pads. Each of the first connection pads includes a first conductive layer disposed on the board, a second conductive layer which entirely overlaps with the first conductive layer in a plan view, is disposed on the first conductive layer and is formed of a different material from that of the first conductive layer, and a third conductive layer entirely overlapping with the second conductive layer and disposed on the second conductive layer.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: January 17, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventor: Joo-Nyung Jang
  • Patent number: 11545597
    Abstract: A light emitting device includes an LED having a (e.g., top) light output surface, a ceramic phosphor, and an adhesive layer positioned to attach the top of the LED to the ceramic phosphor. In one embodiment the adhesive layer is composed of multiple separate patches (regions) that define at least one channel therebetween, with the channel being open to an environment to permit oxygen permeation. The adhesive layer can be applied by a patternable dispensing system.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: January 3, 2023
    Assignee: Lumileds LLC
    Inventors: Daniel Bernardo Roitman, Michael Laughner
  • Patent number: 11545545
    Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: January 3, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Robert Haase, Sylvain Leomant, Maximilian Roesch, Ravi Keshav Joshi, Andreas Meiser, Xiaoqiu Huang, Ling Ma
  • Patent number: 11538893
    Abstract: A display device includes a first display region, a second display region, a curved portion provided between the first display region and the second display region, a plurality of first control lines provided in the first display region and extending in a first direction in which the first display region and the second display region are arranged side by side, and a plurality of second control lines provided in the second display region and extending in the first direction. The first control lines and the second control lines are electrically connected via curved portion wiring lines formed in the curved portion.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 27, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Noriko Watanabe, Takeshi Yaneda
  • Patent number: 11532477
    Abstract: A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: December 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nicholas Hendricks, Adam L. Olson, William R. Brown, Ho Seop Eom, Xue Chen, Kaveri Jain, Scott Schuldenfrei
  • Patent number: 11527590
    Abstract: A light emitting display apparatus according to an exemplary embodiment of the present disclosure includes an insulating layer on a substrate and including a base portion and a protrusion portion having an uneven portion at a part of the base portion, a first electrode covering an upper portion of the base portion and a side portion and a upper portion of the protrusion portion and disposed along the shape of the uneven portion, a bank layer covering a part of the insulating layer and a part of the first electrode, and an emission layer on the first electrode and the bank layer, and a second electrode on the emission layer.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: December 13, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Dongmin Sim, Wonhoe Koo, Hyekyung Choi, YongCheol Kim, Kyunghoon Han, YoungDock Cho
  • Patent number: 11527596
    Abstract: A display device includes a light transmitting substrate in which pixels are arranged, the pixels having a light transmitting region that transmits external light and a light emitting region in which a light emitting element is disposed; a first light blocking layer that is disposed in the light emitting region and blocks the external light; a thin film transistor that is disposed on the first light blocking layer and controls a light emission of the light emitting element; a first insulating layer that covers an active layer of the thin film transistor; a second light blocking layer that is disposed on the first insulating layer so as to cover the thin film transistor and blocks the external light; and a first light blocking wall that is connected to the first light blocking layer and the second light blocking layer and blocks the external light.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: December 13, 2022
    Assignees: TIANMA JAPAN, LTD., WUHAN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Jun Tanaka
  • Patent number: 11527564
    Abstract: A manufacturing method of an image sensor including the following steps is provided. A substrate is provided. A light sensing device is formed in the substrate. A storage node is formed in the substrate. The storage node and the light sensing device are separated from each other. A buried gate structure is formed in the substrate. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. A first light shielding layer is formed on the buried gate. The first light shielding layer is located above the storage node and electrically connected to the buried gate.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: December 13, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
  • Patent number: 11527468
    Abstract: A connection body which comprises a base structure at least predominantly made of a semiconductor oxide material or glass material, and an electrically conductive wiring structure on and/or in the base structure, wherein the electrically conductive wiring structure comprises at least one vertical wiring section with a first lateral dimension on and/or in the base structure and at least one lateral wiring section connected with the at least one vertical wiring section, wherein the at least one lateral wiring section has a second lateral dimension on and/or in the base structure, which is different to the first lateral dimension.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: December 13, 2022
    Assignee: Infineon Technologies AG
    Inventors: Andreas Riegler, Christian Fachmann, Matteo-Alessandro Kutschak, Carsten von Koblinski, Hans Weber
  • Patent number: 11522010
    Abstract: A method of integrating a phase change switch (PCS) into a Bipolar (Bi)/Complementary Metal Oxide Semiconductor (CMOS) (BiCMOS) process, comprises providing a base structure including BiCMOS circuitry on a semiconductor substrate, and forming on the base structure a dielectric contact window layer having metal through-plugs that contact the BiCMOS circuitry. The method includes constructing the PCS on the contact window layer. The PCS includes: a phase change region, between ohmic contacts on the phase change region, to operate as a switch controlled by heat. The method further includes forming, on the contact window layer and the PCS, a stack of alternating patterned metal layers and dielectric layers that interconnect the patterned metal layers, such that the stack connects a first of the ohmic contacts to the BiCMOS circuitry and provides connections to a second of the ohmic contacts and to the resistive heater.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: December 6, 2022
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Patrick B. Shea, Robert M. Young, Keith H. Chung, Andris Ezis, Ishan Wathuthanthri
  • Patent number: 11522144
    Abstract: The present disclosure discloses a stretch display device and a preparation method. The method includes providing a substrate on which a flexible substrate is disposed, and a film layer constituting a thin film transistor disposed on a side of the flexible substrate away from the substrate, the film layer being away from the flexible substrate. One side defines a plurality of pixel regions; a hollow portion is formed between adjacent two of the pixel regions, the hollow portion penetrates through the film layer and the flexible substrate; and thermal separation is provided in the hollow portion via a gel; a light-emitting element is disposed in the pixel region, and an encapsulating film layer is disposed on a side of the light-emitting element and the thermal separation gel away from the flexible substrate; heating the thermal separation gel, and the flexible liner. The bottom and the substrate are peeled off.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: December 6, 2022
    Assignee: Beijing BOE Technology Development Co., Ltd.
    Inventors: Xiaohu Li, Jinxiang Xue, Zhiqiang Jiao
  • Patent number: 11515365
    Abstract: A display panel and a display device are disclosed. The display panel includes an array substrate, a photo spacer layer, and a light-emitting function layer. The photo spacer layer and the light-emitting function layer are sequentially disposed on the array substrate. The display panel includes a display area and a sensor light-receiving area, The light-emitting function layer is disposed in the display area and the sensor light-receiving area. The photo spacer layer includes a plurality of first photo spacers disposed in the display area and a plurality of second photo spacers disposed in the sensor light-receiving area. A distribution density of the second photo spacers is less than a distribution density of the first photo spacers.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: November 29, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Wanghui Guo
  • Patent number: 11515205
    Abstract: One illustrative method disclosed herein includes forming at least one first layer of insulating material above an upper surface of a top electrode of a memory cell, forming a patterned etch stop layer above the at least one first layer of insulating material, wherein the patterned etch stop layer has an opening that is positioned vertically above at least a portion of the upper surface of the top electrode and forming at least one second layer of insulating material above an upper surface of the etch stop layer. The method also includes forming a conductive contact opening that extends through the etch stop layer to expose at least a portion of the upper surface of the top electrode and forming a conductive contact structure in the conductive contact opening, wherein the conductive contact structure is conductively coupled to the upper surface of the top electrode.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: November 29, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Eswar Ramanathan, Sunil Kumar Singh, Xuan Anh Tran, Suryanarayana Kalaga, Juan Boon Tan
  • Patent number: 11508779
    Abstract: A light emitting element includes: a Si substrate including: a first semiconductor layer, a plurality of light emitting layers arranged in a matrix on part of an upper surface of the first semiconductor layer, and a plurality of second semiconductor layers respectively disposed on upper surfaces of the light emitting layers; a first external connection part disposed on the Si substrate at a first end of the Si substrate in a longitudinal direction; a second external connection part disposed on the Si substrate at a second end of the Si substrate opposite to the first end in the longitudinal direction; and a plurality of wiring electrodes disposed on the Si substrate, the plurality of wiring electrodes including a first wiring electrode electrically connected to the first external connection part, and a second wiring electrode electrically connected to the second external connection part.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: November 22, 2022
    Assignee: NICHIA CORPORATION
    Inventor: Hirofumi Kawaguchi
  • Patent number: 11508934
    Abstract: A display device includes, a display region, and a peripheral region arranged outside of the display region, the peripheral region includes, a first inorganic insulating layer, a first organic insulating layer arranged on the first inorganic insulating layer, and a second inorganic insulating layer arranged on the first organic insulating layer, wherein a part of the first inorganic insulating layer in the display region side from a slope of the first inorganic insulating layer is in contact with the second inorganic insulating layer, the slope of the first inorganic insulating layer is exposed at the end part of the periphery region, and includes a bottomed hole with a concave and convex part, and the density of a fluorine ions in the concave and convex part is more than 100 times greater than the density of the fluorine ions in the first inorganic insulating layer arranged in the display region.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 22, 2022
    Assignee: JAPAN DISPLAY INC.
    Inventor: Kyuri Motokawa
  • Patent number: 11502154
    Abstract: Disclosed are a display apparatus and a method for manufacturing the same. The display apparatus comprises: a multi-buffer layer; a pixel array layer formed on the multi-buffer layer and including a plurality of pixels respectively formed as the intersections of a plurality of gate lines and a plurality of data lines; an encapsulation layer formed on the pixel array layer; and an encapsulation substrate formed on the encapsulation layer and including a display area and a non-display area adjacent to the display area, wherein, the encapsulation substrate is for supporting the display area and the non-display area such that there is no base substrate in the display apparatus.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: November 15, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Hoiyong Kwon, MiReum Lee
  • Patent number: 11502116
    Abstract: An imaging sensor includes a pixel array containing photodiodes, the photodiodes being isolated from one another by full thickness deep trench isolations. Row control circuitry controls which rows of the pixel array operate in an imaging mode and which rows of the pixel array operate in an energy harvesting mode, on a row by row basis. Switch circuitry selectively connects different groups of photodiodes in rows operating in the energy harvesting mode into forward biased series configurations between a voltage output line and a ground line, or into forward biased parallel configurations between the voltage output line and the ground line.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: November 15, 2022
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventors: Filip Kaklin, Jeffrey M. Raynor
  • Patent number: 11488911
    Abstract: A flip-chip package substrate is provided. A strengthening structure is provided on one side of a circuit structure to increase the rigidity of the flip-chip package substrate. When the flip-chip package substrate is used in large-scale packaging, the flip-chip package substrate can have good rigidity, so that the electronic package can be prevented from warping.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: November 1, 2022
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chu-Chin Hu, Shih-Ping Hsu