Patents Examined by Vu Anh Le
  • Patent number: 8942054
    Abstract: Memories, systems, and methods for refreshing are provided, such as a memory with an array of memory cells divided into sections. Memories include replacement elements having a digit line, and detecting circuitry coupled to a digit line of at least one section of the memory cell array and coupled to the digit line of the replacement element. Memories include control logic configured to selectively refresh the replacement element at an occurrence when a non-neighboring section of the memory cell array relative to the replacement element is refreshed. Other memories, systems, and methods are provided.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: January 27, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Victor Wong, William F. Jones, Seth A. Eichmeyer
  • Patent number: 6771531
    Abstract: A memory device including a cross point type ferroelectric memory and a randomly accessible write back type cache memory, where the cross point type ferroelectric memory is accessed via a second memory, and a memory system using the same. By this, data in the cache memory can be freely randomly accessed, the cross point type memory is accessed only at miss hits, and the number of data rewrites is greatly reduced.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: August 3, 2004
    Assignee: Sony Corporation
    Inventor: Toshiyuki Nishihara
  • Patent number: 6724656
    Abstract: An electrically alterable, non-volatile memory cell has more than two memory states that can be programmed selectively. Programming of the cell can be performed without actually reading the memory state of the cell during the programming operation. A plurality of the memory cells are preferably arranged in a matrix of rows and columns disposed substantially in a rectangle, with a plurality of word lines coupled with memory gate electrodes intersecting a first side of the rectangle substantially perpendicularly, a plurality of bit lines coupled with memory drain-source current paths intersecting a second side of the rectangle substantially perpendicularly (the second side also substantially perpendicularly intersecting the first side), a row select circuit being disposed at the first side for coupling with the word lines, and peripheral circuitry including a column select circuit and a sense circuit being disposed at the second side.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: April 20, 2004
    Assignee: BTG International Inc.
    Inventor: Gerald J. Banks
  • Patent number: 6714479
    Abstract: The present invention provides a semiconductor memory device and control method capable of effectively suppressing the generation of operating current originating in noise of address signals provided from the outside without impairing the operating speed during reading and writing. This semiconductor memory device is provided with a filter circuit (102) for removing noise contained in address signals provided from the outside, a circuit system containing an ATD circuit (311) for generating a first address transition detection signal (&phgr;ATD1) by detecting a change in an address signal prior to passing through the filter circuit (102), and a circuit system containing an ATD circuit (321) for generating a second address transition detection signal (&phgr;ATD2) by detecting a change in an address signal after passing through the filter circuit (102).
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: March 30, 2004
    Assignee: NEC Electronics Corporation
    Inventors: Hiroyuki Takahashi, Masatoshi Sonoda
  • Patent number: 6711059
    Abstract: According to a first aspect of the present invention, there is provided a memory system having a controller and a non-volatile memory storing firmware for start up and for normal operation of the system, the controller comprising, a volatile memory; and a processor; wherein the controller is arranged to operate during initialization or configuration of the system so that the start up firmware stored in the non-volatile memory is loaded into the volatile memory under hardware control by the controller and with the processor halted, the start up firmware in the volatile memory being subsequently executed by the processor.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: March 23, 2004
    Assignee: Lexar Media, Inc.
    Inventors: Alan Welsh Sinclair, Peter John Smith, Robert Edwin Payne
  • Patent number: 6707751
    Abstract: The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: March 16, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Satoshi Iwahashi, Shigeru Nakahara, Takeshi Suzuki, Keiichi Higeta
  • Patent number: 6667900
    Abstract: Briefly, in accordance with an embodiment of the invention, a method and an apparatus to read a phase change memory is provided, wherein the method includes zero biasing unselected memory cells during reading of a selected memory cell.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: December 23, 2003
    Assignee: Ovonyx, Inc.
    Inventors: Tyler Lowrey, Daniel Xu
  • Patent number: 6643208
    Abstract: A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in access with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: November 4, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadato Yamagata, Kazutami Arimoto, Masaki Tsukude
  • Patent number: 6611445
    Abstract: In a content addressable memory (CAM), a spare CAM word serving as a redundant circuit is mounted in addition to a plurality of CAM words, and a storage section for holding information indicating whether there is a defective CAM word in the plurality of CAM words, and if there is one or more defective CAM word, address information of the defective CAM word. Control is applied according to the address information of the defective CAM word such that the defective CAM word is replaced with the spare CAM word. The search output of the defective CAM word is replaced with that of the spare CAM word. The spare CAM word serving as a redundant circuit is mounted without increasing a circuit scale and an output delay time, and a produce yield is improved.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: August 26, 2003
    Assignee: Kawasaki Microelectronics, Inc.
    Inventors: Naoki Kanazawa, Ryuichi Hata
  • Patent number: 6608784
    Abstract: When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: August 19, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Motoki Kanamori, Kunihiro Katayama, Atsushi Shiraishi, Shigeo Kurakata, Atsushi Shikata
  • Patent number: 6600687
    Abstract: As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: July 29, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Kurt D. Beigel, Manny K. Ma, Gordon D. Roberts, James E. Miller, Daryl L. Habersetzer, Jeffrey D. Bruce, Eric T. Stubbs
  • Patent number: 6563738
    Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.
    Type: Grant
    Filed: May 20, 2002
    Date of Patent: May 13, 2003
    Assignee: Fujitsu Limited
    Inventors: Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi Kawashima, Minoru Yamashita
  • Patent number: 6552933
    Abstract: A memory system including an array of memory cells, a programming voltage node for receiving a first programming voltage, a memory controller which controls memory programming operations on the array of memory cells, and voltage detection circuitry, operably coupled to the memory controller and the programming voltage node, with the voltage detection circuitry being configured to enable the memory controller to initiate one of the programming operations if the first programming voltage exceeds a first voltage level and to continue the programming operation once the programming operation has been initiated if the first programming voltage drops to a second voltage level and to terminate the programming operation once the programming operation has been initiated if the first programming voltage drops below the second voltage level, with the first voltage level being greater than the second voltage level.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: April 22, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 6538915
    Abstract: A semiconductor device includes memory cells of one-transistor one-capacitor connected to n+1 bit lines that are simultaneously driven, sense amplifiers connected to the n+1 bit lines, and a reference voltage generating circuit generates an average voltage of a highest voltage and a lowest voltage among bit line voltages that are obtained by accessing the n+1 bit lines in parallel, and supplying the average voltage to the sense amplifiers as a reference voltage.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: March 25, 2003
    Assignee: Fujitsu Limited
    Inventors: Toru Endo, Shoichiro Kawashima
  • Patent number: 6535435
    Abstract: A reference voltage generation circuit is provided which includes a p-channel type MOSFET used as an input transistor to allow a sufficient current to flow through a differential amplifier even if the threshold voltages of MOSFETs used in the differential amplifier significantly increase. A push-pull conversion circuit is coupled to the differential amplifier and has a double end configuration to provide a sufficiently high level to drive a p-channel output buffer. This arrangement allows a stable operation at a sufficiently low power supply voltage even if the threshold voltages of the MOSFETs forming the differential amplifier are high. It also allows quick activation when the power is turned on and provides high stability.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: March 18, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hitoshi Tanaka, Masakazu Aoki, Shinichiro Kimura, Hiromasa Noda, Tomonori Sekiguchi
  • Patent number: 6525981
    Abstract: A graphics subsystem having a dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM), which has a full-page increment/decrement burst mode. In one embodiment, the DDR SDRAM/SGRAM includes a memory array and a logic circuitry coupled thereto. The graphics subsystem may be formed on a single semiconductor chip. The memory array is addressable by even and odd word addresses. The logic circuitry has a burst increment mode to access the array starting at an even word address and a burst decrement mode to access the array starting at an odd word address.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: February 25, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Kevin J. Ryan
  • Patent number: 5754479
    Abstract: The invention describes a technique in which the performance of a block write operations for SGRAM and VRAM are improved. The technique also produces improved noise margin along the data line when connecting to bit switches under mask during block write operation. The technique rearranges the physical location of each bit switch located along the data lines such that the worse case configuration is not clustered at the end of the data lines during a block write operation. This reduces the voltage drop along the data lines and provides more energy to switch bit lines or the corresponding memory columns. It also produces less drop on the bit lines as a result of doing a mask during the block write operation.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: May 19, 1998
    Assignee: Etron Technology, Inc.
    Inventors: Tah-Kang Joseph Ting, Yung-Ching Hsieh, Chun Shiah