Abstract: A system and method of organically generating a camera-pose map is disclosed. A target image is obtained of a location deemed suitable for augmenting with a virtual augmentation or graphic. An initial camera-pose map is created having a limited number of calibrated camera-pose images having calculated camera-pose locations and homographies to the target image. Then, during the event, the system automatically obtains current images of the event venue and determines homographies to the nearest calibration camera-pose image in the camera-pose map. The separation in camera-pose space between the current images and the camera-pose images are calculated. If this separation is less than a predetermined threshold, that current image is fully calibrated and added to the camera-pose map, thereby growing the map organically.

Abstract: An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC) that is coupled to the resistive memory array. The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

Abstract: A low-dose imaging method includes receiving a sparse image set of a portion of a patient's anatomy; up-sampling the sparse image set, in the sinogram domain and using a first neural network, to yield an up-sampled sinogram; generating, from the up-sampled sinogram, an initial reconstruction; and removing, from the initial reconstruction and using a second neural network, one or more artifacts in the initial reconstruction to yield a final output volume.

Abstract: The invention generally relates to methods for manually calibrating imaging systems such as optical coherence tomography systems. In certain aspects, an imaging system displays an image showing a target and a reference item. A user looks at the image and indicates a point within the image near the reference item. A processer detects an actual location of the reference item within an area around the indicated point. The processer can use an expected location of the reference item with the detected actual location to calculate a calibration value and provide a calibrated image. In this way, a user can identify the actual location of the reference point and a processing algorithm can give precision to the actual location.

Abstract: A neural network system, includes: a processor configured to detect a plurality of object candidates included in a first image, generate metadata corresponding to the plurality of object candidates based on the first image, and set data processing orders of the plurality of object candidates based on the metadata; and at least one resource configured to perform data processing with respect to the plurality of object candidates. The processor is configured to sequentially provide pieces of information related to data processing of the plurality of object candidates to the at least one resource according to the set data processing orders, and the at least one resource is configured to sequentially perform data processing with respect to the plurality of object candidates according to an order in which a piece of information related to data processing of each of the plurality of object candidates is received.

Abstract: Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines with associated decoders. The sockets may be included in sub-blocks of the array. A sub-block may be configured to include sockets for multiple access lines. A socket may intersect an access line in the middle of the access line, or at an end of the access line. Sub-blocks containing sockets for an access line may be separated by a period based on the access line.

Abstract: The present disclosure includes apparatuses, methods, and systems for memory cell programming that cancels threshold voltage drift. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to program a memory cell of the plurality of memory cells to one of two possible data states by applying a first voltage pulse to the memory cell, wherein the first voltage pulse has a first polarity and a first magnitude, and applying a second voltage pulse to the memory cell, wherein the second voltage pulse has a second polarity that is opposite the first polarity and a second magnitude that can be greater than the first magnitude.

Abstract: Implementations are described herein for predicting soil organic carbon (“SOC”) content for agricultural fields detected in digital imagery. In various implementations, one or more digital images depicting portion(s) of one or more agricultural fields may be processed. The one or more digital images may have been acquired by a vision sensor carried through the field(s) by a ground-based vehicle. Based on the processing, one or more agricultural inferences indicating agricultural practices or conditions predicted to affect SOC content may be determined. Based on the agricultural inferences, one or more predicted SOC measurements for the field(s) may be determined.

Abstract: A method and device for detecting circulating abnormal cells. The method for detecting the circulating abnormal cells comprises: respectively segmenting and labelling, by using an image processing algorithm and a morphological algorithm, cell nuclei included in dark field microscope images of a plurality of probe channels (101); inputting the dark field microscope images, in which cell nuclei are labelled, of the plurality of probe channels into a pre-built circulating abnormal cell detection model to acquire the number of staining signals included in each labelled cell nucleus in the dark field microscope image of each probe channel (102); and for each labelled cell nucleus, on the basis of the number of the staining signals included in the labelled cell nucleus in the acquired dark field microscope image of each probe channel, determining whether the labelled cell nucleus belongs to a circulating abnormal cell (103).

Abstract: Provided are a method of providing carbon emission management information, the method comprising extracting, by a carbon emission management information providing server, an area corresponding to a company to be evaluated from satellite image data of the company to be evaluated, calculating, by the carbon emission management information providing server, a greenhouse gas concentration of the area corresponding to the company to be evaluated from the satellite image data, calculating, by the carbon emission management information providing server, a change in vegetation index around the company to be evaluated from the satellite image data, analyzing, by the carbon emission management information providing server, a relationship between carbon emission management factors input in relation to the company to be evaluated, a change in the calculated greenhouse gas concentration, and the calculated change in vegetation index and generating, by the carbon emission management information providing server, carbon emi

Abstract: A clock mode configuration circuit for a memory device. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

Abstract: The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.

Abstract: A data transmission circuit and method, and a storage device are provided. The data transmission circuit includes a serial-parallel conversion module, a comparison module, a data conversion module and a write circuit module. The serial-parallel conversion module receives a plurality of pieces of external data in batches and outputs initial parallel data according to the external data. The comparison module compares the received initial parallel data with global data to output a comparison result. The data conversion module, responsive to that the comparison result indicates that the preset threshold is exceeded, inverts the initial parallel data and transmits the inverted data to a data bus, and responsive to that the comparison result indicates that the preset threshold is not exceeded, transmits the initial parallel data to the data bus. The write circuit module transmits data on the data bus to a global data bus.

Abstract: Systems and methods are disclosed herein for detecting impurities of harvested plants in a receptacle of a harvester. In an embodiment, a harvester controller receives, from a camera facing the contents of the receptacle, an image of the contents. The harvester controller applies the image as input to a machine learning model. The harvester controller receives, as output from the machine learning model, an identification of an impurity of the harvested plants. The harvester controller transmits a control signal based on the impurity.

Abstract: Systems and methods are configured to extract images from provided source data files and to preprocess such images for content-based image analysis. An image analysis system applies one or more machine-learning based models for identifying specific features within analyzed images, and for determining one or more measurements based at least in part on the identified features. Such measurements may be embodied as absolute measurements for determining an absolute distance between features, or relative measurements for determining a relative relationship between features. The determined measurements are input into one or more machine-learning based models for determining a classification for the image.

Abstract: The facial verification apparatus is a mobile computing apparatus, including a camera to capture an image, a display, and one or more processors. While in a lock state, the image is captured and facial verification performed using a face image, or using a detected face and in response to the face being detected. The facial verification includes a matching with respect to the detected face, or obtained face image, and a registered face information. If the verification is successful, the lock state of the apparatus may be canceled and the user allowed access to the apparatus. The lock state may be cancelled when the verification is successful and the user has been determined to have been attempting to gain access to the apparatus. Face image feedback to the user may not be displayed during the detecting for, or obtaining of, the face and/or performing of the facial verification.

Abstract: A semiconductor device is provided. The semiconductor device includes a resistive memory device, and at least a first photodetector and a second photodetector positioned adjacent to the resistive memory device to allow for measurement of the intensity of photon emission from a filament of the resistive memory device.

Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Each access line is formed of a conductive material (e.g., tungsten). The access line includes one or more resistive layers (e.g., tungsten silicon nitride) each having a resistivity greater than the resistivity of the conductive material used to form the access line. The resistive layers are formed overlying or underlying at least a portion of the memory cells. A driver is electrically connected to the access line using a via. The driver generates a voltage on the access line to access the memory cells.

Abstract: The present disclosure relates to a three-dimensional memory (3D) and a control method thereof. The 3D memory includes a first deck and a second deck which are stacked in a vertical direction of a substrate. The first deck and the second deck each includes a plurality of memory string. Each memory string includes a plurality of memory cells. The plurality of memory cells includes a first portion and a second portion. A diameter of channel structure corresponding to the first portion of memory cells is smaller than that of channel structure corresponding to the second portion of memory cells. The method includes performing a read operation for selected memory cells that are in at least one of the first deck or the second deck; and applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck. A first pass voltage is lower than a second pass voltage.

Abstract: A semiconductor device may include first row lines each extending in a first direction, column lines each extending in a second direction crossing the first direction, second row lines each extending in the first direction, a plurality of first memory cells respectively coupled between the first row lines and the column lines, each of the plurality of first memory cells including a first variable resistance layer and a first dielectric layer positioned between the first variable resistance layer and a corresponding one of the first row lines, and a plurality of second memory cells respectively coupled between the second row lines and the column lines, each of the plurality of second memory cells including a second variable resistance layer and a second dielectric layer positioned between the second variable resistance layer and a corresponding one of the second row lines.