Patents Examined by W. C. Tupman
  • Patent number: 4182023
    Abstract: A method of manufacturing a silicon gate MIS device providing automatic formation and alignment of the gate structure during formation of adjacent impurity regions. In a preferred embodiment, the process is for the gate structure and source and drain of silicon gate FETs. The layered gate constituents-- typically oxide and silicon-- are formed on a semiconductor wafer. A photoresist mask which is larger than the desired gate size is formed on the silicon and the silicon is etched to a predetermined size beneath the overhanging mask. A deposition mask in the form of the photoresist mask or the gate silicon oxide and which is of the same size as the photoresist mask, is used to control the deposition of impurities within predetermined surface areas of the substrate which are spaced a predetermined distance from the silicon gate boundaries.
    Type: Grant
    Filed: October 21, 1977
    Date of Patent: January 8, 1980
    Assignee: NCR Corporation
    Inventors: Jerome Cohen, Peter C. Chen
  • Patent number: 4182025
    Abstract: In the manufacture of a monolithic light-emitting diode array, electrical isolation between the n-type regions of portions of the array, for example the columns of a matrix array, is effected by mechanically cutting channels between the portions, through the n-type region and the common electrode. This method of forming the isolation channels makes it possible to produce much narrower channels than can be achieved by chemical etching, thus providing a high resolution array.
    Type: Grant
    Filed: September 28, 1977
    Date of Patent: January 8, 1980
    Assignee: Elliott Brothers (London) Limited
    Inventor: Dennis K. Wickenden
  • Patent number: 4179794
    Abstract: On a common semiconductor wafer constituted by a PN-lamination are formed a number of semiconductor device units. Recessed grooves are formed into this wafer by an etching technique at such sites as one corresponding to the boundaries of the respective adjacent semiconductor device units. To protect the PN-junctions of the wafer exposed on the etched grooves, these surfaces are coated with a thermo-setting resin. Thereafter, the semiconductor wafer is severed apart at the respective recessed grooves into respective individual chips of semiconductor devices.
    Type: Grant
    Filed: April 5, 1978
    Date of Patent: December 25, 1979
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventors: Masao Kosugi, Takashi Ogata
  • Patent number: 4179793
    Abstract: A method of making a charge transfer device which has charge transfer portions arranged in a semiconductor substrate, each of said charge transfer portions having electrodes, and in which an effective asymmetrical potential is produced in each of the charge transfer portions in a carrier transfer direction by the affect of the potential of channel stopper regions upon charge transfer.
    Type: Grant
    Filed: October 12, 1977
    Date of Patent: December 25, 1979
    Assignee: Sony Corporation
    Inventor: Yoshiaki Hagiwara
  • Patent number: 4179792
    Abstract: An enhancement type, self-aligned silicon gate complementary metal oxide semiconductor (CMOS)/silicon on sapphire (SOS) structure is made by generating all gate oxides and oxide isolated regions with dry oxygen at pressures above 1 atmosphere and at temperatures of 800.degree. C. to 825.degree. C. using ion implantation for all doping operations and plasma definition of all masking dielectrics.
    Type: Grant
    Filed: April 10, 1978
    Date of Patent: December 25, 1979
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Sidney Marshall, Robert J. Zeto
  • Patent number: 4178674
    Abstract: A process for forming an electrical contact region between layers of polysilicon with an integral polysilicon resistor during the fabrication of MOS integrated circuits is disclosed. The contact region which does not require critical alignments, may be formed directly over an active channel or buried (substrate) contact. A silicon nitride mask is formed at the location of the contact region on the first polysilicon layer thereby allowing a thick oxide to be grown on the remainder of the substrate. After removal of the silicon nitride mask, a second polysilicon layer is formed which contacts the first layer at the contact region and defines the resistor. A doping step is used to establish the resistance of the resistor. The process permits the fabrication, by way of example, of a static (bistable) MOS memory cell employing polysilicon loads with an area of approximately 1.5 mils.sup.2.
    Type: Grant
    Filed: March 27, 1978
    Date of Patent: December 18, 1979
    Assignee: Intel Corporation
    Inventors: Sheau-Ming S. Liu, William H. Owen, III, Richard D. Pashley
  • Patent number: 4176443
    Abstract: A silicon wafer, having a front surface with disjointed contact areas and a uniform rear surface, is provided at the contact areas of its front surface with respective pads each comprising a base layer of aluminum, a first intermediate layer of chromium or titanium, a second intermediate layer of nickel and an outer layer of gold or palladium. The rear surface is covered with a base layer of gold (or of a gold/arsenic alloy in the case of N-type silicon), a first intermediate layer of chromium, a second intermediate layer of nickel and an outer layer of gold or palladium to which a film of low-melting bonding agent (lead/tin solder) is applied. After testing and elimination of unsatisfactory wafer sections, the remaining sections are separated into dies placed on a conductive substrate; an extremity of a respective terminal lead, encased in a similar bonding agent, is then placed on the outer layer of each contact pad. All soldering operations are simultaneously performed in a furnace.
    Type: Grant
    Filed: November 3, 1978
    Date of Patent: December 4, 1979
    Assignee: SGS-ATES Componenti Elettronici S.p.A.
    Inventors: Giulio Iannuzzi, Carlo C. deMartiis, Vittorio Del Bo, Luciano Gandolfi
  • Patent number: 4175317
    Abstract: In a method for manufacturing a junction type field-effect transistor, there is formed a gate region having one portion over which a source electrode extends and the other portion which allows an essential gate function. These portions are formed by diffusing impurities through openings of different masks.
    Type: Grant
    Filed: November 22, 1977
    Date of Patent: November 27, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Kiyoshi Aoki, Hisao Kamo
  • Patent number: 4173818
    Abstract: A method, including a sequence of process steps, for fabricating insulated gate field effect transistors having very short effective channel lengths. In a first version of the method, the source and drain regions of the device are opened in one process step and self-alignment of the source and the drain to the gate is achieved in one masking step. The drain region is then masked and the source side of the channel is implanted to adjust the threshold voltage of the high threshold voltage channel region. In a second version of the method, the source region is opened and self-aligned with the gate prior to the opening of drain region. Implantation to adjust the threshold voltage of the high threshold voltage channel region takes place before the drain region is opened, and then the drain region is opened and self-aligned with the gate in a further masking step. In either version, the threshold voltage is adjustable and the channel length is controlled to be a small value.
    Type: Grant
    Filed: May 30, 1978
    Date of Patent: November 13, 1979
    Assignee: International Business Machines Corporation
    Inventors: Ernest Bassous, Tak H. Ning, Carlton M. Osburn
  • Patent number: 4173819
    Abstract: A dynamic Random Access Memory consisting of pairs of adjacent one transistor/one capacitor memory cells. The gate electrodes of the MOS FETS in each pair of adjacent memory cells are coupled and further connected to an address line at only a single contact hole. There is also disclosed a method for manufacturing the dynamic Random Access Memory with a high integration density. The gap between one electrode of the capacitor and the MOS FET is minimized by converting the end portion of the capacitor electrode to a thin insulating film.
    Type: Grant
    Filed: August 4, 1978
    Date of Patent: November 13, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventor: Hiroyuki Kinoshita
  • Patent number: 4170818
    Abstract: A barrier height voltage reference includes two field-effect transistors which are substantially identical except for their gate-to-channel potential barrier characteristics and which are biased to carry equal drain currents at equal drain voltages. The resulting difference in potential between the gate contacts of the two field effect transistors produces a voltage reference which is substantially independent of operating point, supply potential, and temperature.
    Type: Grant
    Filed: October 3, 1977
    Date of Patent: October 16, 1979
    Assignee: Hewlett-Packard Company
    Inventors: Morley C. Tobey, Jr., David J. Giuliani, Peter B. Ashkin
  • Patent number: 3939554
    Abstract: A surface thermocouple assembly including a metal sheath having thermocouple conductors extending therethrough in spaced relation from each other and from the sheath by electrical insulating material, an opening in the sheath wall at the hot junction end and through which the conductors are extended, a ceramic plug receiving the conductors and mounted in the opening, a fusion weld of the conductors outside the plug, and a V-shaped pad with a knife-shaped edge integrally formed at the junction end. The thermocouple is made from a length of sheathed thermocouple conductors by forming a keyhole slot at the junction end, removing the insulation around the conductors, bending the conductors through the opening of the keyhole slot, mounting a ceramic plug in place, fusion welding the ends of the conductors outside the plug to define the thermojunction, inserting a metal end plug at the junction end, welding closed the slot and the end plug in position, and building up a V-shaped welded pad at the hot junction end.
    Type: Grant
    Filed: December 4, 1974
    Date of Patent: February 24, 1976
    Assignee: Thermo-Couple Products Company, Inc.
    Inventor: Philip F. Finney