Abstract: A method of fabricating gallium arsenide circuits or devices in which source and drain contact areas are deposited using vapor phase epitaxy techniques through holes in a refractory mask. Selected areas of a refractory mask are etched away to expose a region of active gallium arsenide material in which holes are formed by a chemical or plasma etch. These holes are then filled with highly doped vapor phase epitaxially grown gallium arsenide to provide drain and source contact regions. In further steps additional regions of the refractory mask are etched away to define gate regions. Metallization and lift-off may then occur in a single step to provide contacts to gate, drain and source regions and a planar surface for further device processing.

Abstract: The method of manufacture of a semiconductor device having wirings or electrodes of silicide formed by: exposing parts of a single-crystal silicon layer formed on an insulating substrate, forming a film of metal over the exposed parts, and annealing so that a silicide is formed of the silicon and metal throughout the entire thickness of the silicon layer. The single-crystal silicon layer may be formed on a sapphire or spinel substrate having a film of silicon dioxide, sapphire or spinel, epitaxially grown on a silicon substrate.

Abstract: When growing GaAs by molecular beam epitaxy (MBE), a typical related reaction acts to affix Ga.sub.2 O.sub.3 to the growth surface and hence incorporates such oxide contaminants in the epitaxial layer as it is grown. Such contaminants may yield crystals of poor electrical and optical properties. When Al is added to the Ga source crucible, the Ga.sub.2 O flux is reduced substantially thereby suppressing the formation of such oxide contaminants and remove a serious constraint to MBE growth. When doping GaAs with Mg to form a p-type GaAs layer, unity Mg doping efficiency is achieved by including 0.1% Al in the Ga effusion cell. Such an inclusion of Al improves the Mg doping efficiency by suppressing the formation of MgO, and allows MBE growth at lower substrate temperatures and at higher growth rates.

Abstract: A self-aligned metal process is described which achieves self-aligned metal silicon contacts and micron-to-submicron contact-to-contact and metal-to-metal spacing by use of the pattern of dielectric material having a thickness in the order of a micron or less. The pattern of recessed oxide isolation to device area is also self-aligned by this process. The process results in substantially planar integrated circuit structure. The process is applicable to either a bipolar integrated circuit either bipolar or MOS field effect transistor integrated circuits.

Abstract: A low-pressure, low-temperature organometallic chemical vapor deposition (OM-CVD) method for depositing a doped epitaxial layer of a II-VI compound, such as, n-ZnSe, on a substrate in the deposition zone of an OM-CVD reactor. For example, low-resistivity n-type ZnSe with p<0.05.OMEGA..cm and n>10.sup.17 cm.sup.-3 may be grown epitaxially on (100) GaAs substrates by this method using aluminum as a dopant from a triethylaluminum source. The as-grown layers show a strong near-bandgap photoluminescence peak. The much weaker photoluminescence intensity at longer wavelength indicates that the concentration of deep centers is lower than in doped ZnSe prepared by other prior art methods. Also, no further or post treatment (diffusion or annealing) after growth is necessary.

Abstract: An I.sup.2 L type semiconductor device having an elementary region which is isolated by V-shape grooves from the other portions of the device, said semiconductor device comprising an insulating layer coating covering the surface of the semiconductor body of the device, wherein an injector region is formed under said insulating layer and surrounded by thicker portions of said insulating layer, and base regions are formed under said insulating layer between said thicker portions of said insulating layer and said V-shape grooves.

Abstract: A method of manufacturing an integrated circuit having at least an insulated gate field effect transistor (IGFET). Provided on the silicon surface are successively a gate oxide layer and a doped silicon layer which are patterned by etching by means of a silicon nitride-containing mask which comprises the gate electrode(s) and interconnections. Nitrogen ions are implanted in the surface parts not underlying the mask. By thermal oxidation only the edges of the silicon pattern are oxidized. By ion implantation the source and drain zones are formed, the gate electrodes serving as an implantation mask. If desired, the threshold voltage may then be adjusted by ion implantation in the channel region via the gate electrode.

Abstract: A first compound semiconductor layer is epitaxially formed on a surface of a semi-insulating substrate. The first semiconductor layer is then removed and a second compound semiconductor layer is epitaxially formed on the substrate surface which is now exposed.

Abstract: An integrated circuit structure and process for fabricating it are described which allow fabrication of a very compact high-speed logic gate. The structure utilizes a bipolar transistor formed in an epitaxial silicon pocket surrounded by silicon dioxide. A pair of Schottky diodes and a resistor are formed outside the epitaxial pocket on the silicon dioxide and connected to the pocket by doped polycrystalline silicon.

Abstract: Method of fabricating monolithic integrated circuit structure incorporating a bipolar transistor and a high value resistor. First and second N-type sectors are formed in an N-type epitaxial layer by junction isolation. A silicon oxide layer is formed on the surface of the body. The layer is thinner over a part of the first sector and over a part of the second sector. A layer of silicon nitride is formed on portions of the thinner silicon oxide to overlie predetermined zones within each sector. P-type conductivity imparting material is ion implanted through the unprotected thinner silicon oxide to form a low resistivity region in the first sector and two low resistivity regions in the second sector. The layer of silicon nitride overlying the predetermined zone in the second sector is removed, and an opening is formed over the predetermined zone in the second sector.

Abstract: Disclosed is a method for manufacturing a semiconductor device. In this method an oxidation-resistive insulating film is formed on a silicon body of a one conductivity type. A first impurity region of the opposite conductivity type is selectively formed in said semiconductor body before or after said insulating film is formed. Part of said insulating film which corresponds to part of said first impurity region is etched and exposed portions of said silicon body are etched by isotropic etching to a predetermined depth, using said oxidation-resistive insulating film as a mask. An impurity of the opposite conductivity type is doped into said first impurity region, using said insulating film as a mask, so that a second impurity region of the opposite conductivity type whose concentration is higher than a concentration of said first impurity region is formed in said first impurity region and said silicon body.

Abstract: A vertical PNP bipolar transistor structure with Schottky Barrier diode emitter is disclosed which simplifies the structure and process steps for combining a complementary PNP in an NPN integrated circuit and improves the speed and density of the vertical PNP. The PNP emitter is formed with a Schottky contact such that only the PNP base region is contained in the NPN emitter junction structure. The structure uses a separately masked ion/implant for the NPN intrinsic base implant which also forms the PNP collector region so that the PNP base doping profile can intercept the PNP collector profile at a lower concentration resulting in lower collector/base capacitance, lower series collector resistance and higher collector/base breakdown voltage for the PNP. Since the base doping concentration is lower in the structure and the emitter has no sidewall capacitance, the PNP emitter-base capacitance is greatly reduced. These features result in an improved frequency response for the PNP structure.

Abstract: A method of making an integrated circuit is described. The method includes providing a substrate of single crystal silicon semiconductor material having low minority carrier lifetime, forming an insulating layer of silicon dioxide overlying a major surface of the substrate, forming a plurality of apertures in the insulating layer which expose a plurality of selected portions of the major surface of the substrate, and epitaxially growing a layer of silicon on each of the selected portions of the major surfaces of the substrate.

Abstract: Spaced recesses are formed in a surface of a low impurity concentration P type single-crystal substrate by using a mask. A P type impurity is diffused at a high concentration into an entire surface of the substrate including the recesses to form a P type diffused layer, and an N type layer is epitaxially grown on the P type diffused layer. Then, mask layers are formed on bottom surfaces of the recesses in the epitaxially grown N type layer and this N type layer is anisotropically etched by using the mask layers to form island regions in the recesses. After removing the mask layers, N type diffused layers are formed to cover the island regions. An insulating film (SiO.sub.2) acting to isolate completed transistor elements is formed on the P and N type diffused layers, and a polycrystalline silicon layer acting as a support of a dielectrically isolated integrated circuit device is formed on the insulating film.

Abstract: A method for producing a bipolar transistor which has no emitter-base short and which attains a high density of integration. The method comprises the steps of forming a polycrystalline silicon layer on an anti-oxidation masking layer formed on a base region, selectively etching the polycrystalline silicon layer to form an opening, introducing impurities into the base region to form an emitter region, converting the polycrystalline silicon layer into an oxide layer whereby the size of the opening is reduced, selectively etching the anti-oxidation masking layer to form an emitter electrode opening, and forming electrodes.

Abstract: Silicon doping of GaAs epitaxial layers grown using the AsCl.sub.3 /H.sub.2 /GaAs:Ga CVD system is accomplished using AsCl.sub.3 :SiCl.sub.4 liquid doping solutions. These solutions can be readily prepared with reproducible compositions and provide excellent doping control. Fine adjustments in the doping level can be achieved by adjusting the H.sub.2 flow rate and by varying the temperature of the doping solution. Doping levels may range from about 5.times.10.sup.15 to 5.times.10.sup.19 cm.sup.-3 by adjusting the mole fraction of SiCl.sub.4 in the doping solution and the H.sub.2 flow rate to change the mole fraction of P.sub.HCl. The epitaxial layers doped using this technique have excellent room temperature and liquid nitrogen mobilities for electron concentrations between 1.times.10.sup.16 cm.sup.-3 and 8.times.10.sup.18 cm.sup.-3. This doping method is particularly useful for the growth of GaAs epitaxial layers for FET devices.

Abstract: A method for manufacturing a semiconductor integrated circuit includes diffusing an impurity of a second conductivity type into polycrystalline silicon layers formed on a first conductivity region in a substrate to form second conductivity regions, the polycrystalline silicon layers constituting first electrode wirings to the second conductivity regions; forming a thick oxidation film on the polycrystalline silicon layers and a thin oxidation film on the exposed surface of the substrate by a heat oxidation treatment; and removing the thin oxidation film to form a second electrode wiring to the first conductivity region, said second electrode wiring being insulated from the polycrystalline silicon layers by the thick oxidation film. The method provides integrated circuits such as I.sup.2 L circuits which are capable of high speed operation and a high packaging density.

Abstract: An integrated circuit device is provided in which an I.sup.2 L element and linear transistor are formed on a single chip such that they coexist. In this device, the base and collector regions of a vertical transistor of the I.sup.2 L element are formed such that they are deeper than the base and emitter regions of the linear transistor.

Abstract: A fabrication process for a gallium arsenide MESFET device is disclosed. A feature of the invention is placing a gate structure on the gallium arsenide substrate. Then a process including molecular beam epitaxy, grows epitaxial gallium arsenide on each respective side of the gate, forming a raised source region and a raised drain region. Gallium arsenide will not grow in a conductive state on top of a tungsten gate metal. The resulting MESFET device has a raised source and drain which significantly reduces the high resistance depleted surface adjacent to the gate which generally occurs in planer gallium arsenide MESFET devices. Furthermore, the MESFET channel region which is defined by the proximate edges of the source and the drain, is self-aligned with the edges of the gate by virtue of the insitu process for the formation of the source and drain, as described above.

Abstract: In the production of a semiconductor integrated circuit device including a selective oxidation step at a high temperature using a nitride film as a mask for isolating respective element regions in a semiconductor wafer with oxidized regions, electrode contact regions and active regions are successively formed in each element region to be surrounded by the oxidized regions and thin oxide films are formed on exposed surfaces of the electrode contact regions, the thin semiconductor oxide films are removed simultaneously by immersed etching, and then electrode metal layers are formed thereon. The thickness of the oxide layer on which the electrode metal layers are formed is maintained almost uniform to ensure the isolation effect. Since a buried region in each element region is required only to make partial contact with the contact region at the bottom portion, the integration density of the elements in the integrated circuit can be increased.