Abstract: In a memory array wherein each cell includes an emitter follower, a diode is formed on the emitter by a thin layer which is capable of being shorted by vertical migration of bit line atoms through the layer and into the emitter region. The thin layer is fabricated by epitaxially growing the thin layer over the wafer with the emitter diffusion aperture open, oxidizing the epitaxial layer, selectively removing portions of the polycrystalline epitaxial layer and removing the oxide from the remaining epitaxial layer in the emitter diffusion aperture.

Abstract: This disclosure relates to a high power VMOS semiconductor device and fabrication method therefor. This VMOS semiconductor device uses a doped polysilicon gate electrode in the V groove and an overlying metal electrode located over an insulation layer protecting the doped polysilicon gate electrode. This overlying metal electrode layer covers substantially the entire surface area (except for a small area where electrical contact is made to the doped polysilicon gate electrode) of one surface of the device.

Abstract: A process for fabricating an electrically erasable nonvolatile memory cell comprises forming a first region of insulating material which is less than about 200 Angstroms thick on a selected surface portion of an electrically-isolated relatively lightly doped pocket of epitaxial silicon of a first conductivity type such that first and second surface areas of the epitaxial pocket are exposed. Regions of the epitaxial pocket underlying the first and second exposed surface areas are doped such that first and second relatively lightly doped regions of a second conductivity type are formed in the epitaxial pocket. Relatively heavily doped polysilicon regions of the first conductivity type are formed on the first insulating region and on the second relatively lightly doped epitaxial region.

Abstract: A self-aligned method of implanting the edges of NMOS/SOS transistors is described. The method entails covering the silicon islands with a thick oxide layer, applying a protective photoresist layer over the thick oxide layer, and exposing the photoresist layer from the underside of the sapphire substrate thereby using the island as an exposure mask. Only the photoresist on the islands' edges will be exposed. The exposed photoresist is then removed and the thick oxide is removed from the islands edges which are then implanted.

Abstract: In the present invention, an epitaxial layer of a doped III-V alloy is grown on a semiconductor substrate by a molecular beam epitaxy process using a molecular beam of lead together with molecular beams of the constituent elements of the doped III-V alloy. The magnitude of the lead flux is sufficient to form and maintain a presence of from 5 to 20% of a monolayer of lead on the growth surface. The technique is directed particularly to ternary and quaternary III-V compositions.

Abstract: Dielectrically isolated areas of single crystalline silicon suitable for use in device applications have been produced utilizing a particular processing sequence. This sequence first involves producing an area of porous silicon on a silicon substrate. A single crystal region of silicon is then formed on the porous silicon through procedures such as molecular beam epitaxy, chemical vapor deposition or laser fusion. The region of the porous silicon under the single crystal silicon is then oxidized in a specifically controlled manner to form an insulator.

Abstract: A method of manufacturing a semiconductor device, which comprises the steps of forming a first high impurity concentration region of a conductivity type opposite to the conductivity type of a semiconductor substrate in the substrate along the principal surface thereof, depositing a first epitaxial layer of the same conductivity type as the substrate on the entire principal surface thereof, forming a low impurity concentration region of the opposite conductivity type to the substrate in the first epitaxial layer along a surface portion thereof corresponding to the first high impurity concentration region, forming a second high impurity concentration region of the opposite conductivity type to the substrate in the first epitaxial layer along a different surface portion thereof, forming a second epitaxial layer of the opposite conductivity type to the substrate on the first epitaxial layer, thermally treating the resultant intermediate device to cause diffusion of the impurities in the first and second high impu

Abstract: A layer of material such as the metal base of a transistor is embedded in single crystal. A layer of the material with small, uniformly dimensioned and uniformly spaced openings is formed on a single crystal substrate, and the single crystal is grown from the exposed portions of the substrate over the layer of material. For best results, the layer of material to be embedded is deposited relative to the crystal orientation to provide a much greater rate of crystal growth laterally across the layer than away from the crystal substrate. The method is particularly useful in fabricating a permeable base transistor having slits formed in the metal base layer. An integrated circuit can be fabricated by forming a pattern of conductive material on a single crystal, that pattern having continuous regions which inhibit further crystal growth and narrow regions or regions having openings therein which permit lateral crystal growth across those regions.

Abstract: Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.

Abstract: A method of manufacturing a mixed crystal compound semiconductor wafer suitable for the production of LED having a high light output. Upon a monocrystalline substrate of III-V semiconductor material a base layer is epitaxially grown of the same material as the substrate. An initial gradient layer is grown on the base layer having a mixed crystal ratio varying continuously from that of the base layer to a first value at a constant temperature. A combination sublayer is grown on the initial gradient sublayer which includes at least one constant sublayer having a constant crystal mixture ratio and at least one gradient sublayer having a crystal mixture ratio varying continuously between the mixed crystal ratios of its adjacent constant layers.

Abstract: A method for manufacturing a semiconductor transistor device, specifically a Schottky barrier gate field-effect transistor, having an excellent performance at high frequency due to an exceedingly short gate length. An electrically conductive active layer is formed on a semi-insulating semiconductor substrate. Two adjacent walls are formed on the adjacent layer, are made of resist material, and extended linearly parallel to one another. Ohmic electrode metal is then evaporated obliquely with respect to the vertical surfaces of the two walls to form an ohmic electrode layer on the active layer in areas except for that lying between the two walls. A layer of Schottky barrier metal is then deposited between the two walls, and then the two walls are removed to remove the layers of ohmic electrode metal and Schottky barrier metal on the two walls.

Abstract: A monolithic charge-coupled infrared imaging device (CCIRID) is fabricated on N-type HgCdTe. A native oxide layer on the semiconductor is used, in combination with ZnS to provide first level insulation. An opaque field plate over first level insulation is provided for signal channel definition. Second level insulation (ZnS) is substantially thicker than the first level, and is provided with a stepped or sloped geometry under the first level gates. Input and output diodes are provided with MIS guard rings to increase breakdown voltages.

Abstract: A method of making a semiconductor device which includes at least one pair of complementary vertical bipolar transistors formed on a plate having a substrate formed of two adjacent portions of opposite conductivity type forming a p-n junction therebetween. The two adjacent portions form, respectively, the collector region of a first of the transistors and the emitter region of a second of the transistors. An electrode is provided on the lower face of the substrate to connect together the two adjacent portions of the substrate. The method of the invention is particularly applicable to making mixed Darlington amplifier structures and push-pull amplifiers composed of such structures.

Abstract: A method of manufacturing a semiconductor device characterized in that after a fine groove has been formed in the surface of a semiconductor layer by dry etching, an insulating region is formed so as to fill up the fine groove.

Abstract: A silicon-on-sapphire semiconductor structure, and method of fabricating such structure, in which a silicone nitride layer is provided over the oxide layer. The silicon nitride layer is disposed over the upper edge of the silicon island, and acts to prevent gate oxide breakdown.

Abstract: Disclosed is a process for reducing microcracks and microvoids in the formation of polycrystalline (polysilicon) structures from initial layers of amorphous silicon by annealing. In annealing of amorphous silicon to the polycrystalline form, the crystal grains are thickness limited; and thus by maintaining the thickness below 1000 angstroms, the spacing between contrasting material forming the crystal grains can be minimized on anneal. The resultant equiaxial grains are used as seed crystals for epi-like growth of silicon from them into the required or desired layer thickness.

Abstract: Low-resistance diffused regions useful as current-supply paths in IC MOS semiconductor circuits in silicon-gate technology are produced by forming a metal silicide on a doped polysilicon layer positioned on a substrate, applying a SiO.sub.2 layer over the silicide layer, structuring the resultant SiO.sub.2 -silicide-polysilicon triple layer in such a manner that areas of the substrate where the low resistance diffused regions are desired remain covered, thereafter executing gate oxidation and completing fabrication of the desired circuit.

Abstract: A method and apparatus is described for producing Ge or a Ge.sub.1-x Si.sub.x heteroepitaxy film on Si by depositing films of Ge or Ge.sub.1-x Si.sub.x on Si and subjecting the body so formed to a controlled temperature environment, wherein the body is rapidly (within a time period t.sub.o of more than about 100 microseconds) brought to a predetermined temperature within the alloy range of the deposited film but less than the melting point of Si. The body is then held at such temperature for a relatively short time not to exceed about 3 minutes, including the time period t.sub.o.

Abstract: A method of forming a mesa in a semiconductor device comprises forming a plurality of such devices on a wafer, mechanically cutting relatively wide channels to a predetermined depth in said wafer at positions around individual ones of the devices to partially separate the devices from each other. The mechanical cutting technique defines mesa walls and plain surfaces between individual devices. These channels are then etched to repair scars caused by the cutting technique and, thereafter, the wafer is broken along the center line of the channels to separate the devices from each other.

Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The intrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing.