Abstract: A method of manufacturing a device in a wafer with a P-type semiconductor, includes forming on a surface of the semiconductor body a layer of silicon dioxide doped with an N-type dopant. The portion of the doped silicon dioxide covering the interconnect work site area is removed and a masking layer of an oxidation impervious medium is formed over the wafer and thereafter removed from the field areas, as is the doped silicon dioxide layer. A thin layer of gate oxide is formed over the field areas. A layer of conductive polysilicon is formed over the entire wafer followed by a layer of oxygen impervious masking medium. The conductive polysilicon and masking medium layers are removed from all areas of the wafer except those whereat transistors are to be formed. The wafer is exposed to an oxidizing environment under an elevated temperature producing a field oxide over the exposed gate oxide.

Abstract: A high sheet resistance structure for high density integrated circuits and the method for manufacturing such structure is given. The structure includes a silicon region separated from other silicon regions by a dielectric barrier surrounding the region. A resistor of a first conductivity, for example, N type, encompasses substantially the surface of the silicon region. Electrical contacts are made to the resistor. A region highly doped of a second conductivity, for example, P-type, is located below a portion of the resistor region. This region of second conductivity is connected to the surface. Electrical contacts are made to this varied region for biasing purposes. A second region within the same isolated silicon region may be used as a resistor. This region is located below the buried region of second conductivity. Alternatively, the described resistor regions can be connected as transistors.

Abstract: The application discloses a method of terne coating, and a terne coated product, wherein the tin content of the terne is substantially lower than in conventional terne, without the need for other alloying elements in substitution for tin, such as zinc, antimony, silver, and phosphorus. The tin content of the terne bath is lowered below conventional percentages, to between about 2% and about 6.5% and the terne coated product, upon emerging from the coating bath, is jet finished. Such a terne coat has improved solderability and appearance with no change in pinhole frequency. Coating weight control is easier than with a terne coat having 7% or more tin in the bath.

Abstract: A method of producing integrated MOS circuits via silicon gate technology with self-adjusting contacts by using silicon nitride masking. In accordance with this method, after etching contact holes for the formation of contacts between monocrystalline doped regions (5) and polysilicon regions (4, 8), or metal interconnections (12), an insulating layer 10 is produced. This insulating layer is produced, after appropriate masking with an oxidation-inhibiting silicon nitride layer of the regions to be connected, from a layer (8) which is additionally applied and doped to correspond to the doped regions in the silicon substrate, and which is converted by local oxidation into the insulating layer (10). This process provides extremely high packing density of circuit elements.

Abstract: A thin-film single-crystal infrared detector exhibiting an increased frequency of response. A closed transverse junction, formed by diffusing a central electrode of an impurity rich metal into a lead-salt film epitaxially grown on an insulating substrate, provides an effective optical area in excess of the junction surface. An ohmic contact is spaced apart from the central electrode. Junction capacitance, a limitation upon the electrical response, is diminished by the detector geometry while detectivity is enhanced. In an alternative embodiment the detector may be segmented to provide directional detection.

Abstract: An improved dielectric insulator separated substrate for semiconductor integrated circuits is obtained by forming a lamination of at least three thin-polycrystalline layers and dielectric films interposed therebetween on a thick polycrystalline layer of the substrate. A thickness x(.mu.m) of each of the thin-polycrystalline layers is represented by the formula:x.ltoreq.y/40where y is an ultimate thickness of the substrate. By employing the lamination, it is possible to avoid curveness deformation of the substrate due to oxygen diffusion into an exposed polycrystalline layer during doping of an impurity into island regions independently supported by said thick polycrystalline layer.

Abstract: Disclosed is a self-aligned process for providing an improved bipolar transistor structure.The process includes the chemically etching of an intermediate insulating layer to undercut another top layer of a different insulating material in a self-aligned emitter process wherein the spacing of the emitter contact to the polysilicon base contact is reduced to a magnitude of approximately 0.2 to 0.3 micrometers. In addition, in the process an emitter plug is formed to block the emitter region from the heavy P+ ion dose implant of the extrinsic base.

Abstract: A process for preparing semiconductor pellets from one sheet of a semiconductor wafer is disclosed. In the process of the invention, the semiconductor wafer is divided into a plurality of pellet-forming regions and reinforcing regions are formed between the pellet forming regions and at the peripheral part of the wafer.The reinforcing regions prevent breakage of the wafer without increasing the thickness of the pellets whereby a wafer having a large diameter can be used to obtain many pellets having suitable characteristics from one sheet of the wafer without substantial loss.

Abstract: Specific impurity concentration regions are used for the simultaneous formation of CMOS devices and complementary bipolar transistors to produce high voltage, high performance bipolar transistors. The last diffusion step for shallow P.sup.+ and N.sup.+ emitter regions and contact regions is performed without a separate diffusion cycle. The formation of the gate oxide at a relatively low temperature is followed immediately by the formation of an undoped polysilicon gate layer. The polysilicon gate layer is doped to a reasonable resistance and also forms a first level interconnect. Phosphorous doped CVD silicon oxide is formed thereover and the top surface is treated with additional phosphorous to produce tapered contact apertures therethrough when etched. A layer of metal is applied and delineated to form contacts to the substrate regions and to form the second level of interconnects.

Abstract: Surface recombination current in GaAs devices is reduced by means of a semi-insulating, oxygen, iron or chromium doped monocrystalline layer of AlGaAs grown by MBE. The AlGaAs layer is grown on a GaAs body and is then masked. Diffusion of suitable impurities through a window in the mask converts the exposed portions of the AlGaAs layer to low resistivity and modifies the conductivity of the underlying zone of the GaAs body. The peripheral portions of the AlGaAs layer, however, remain semi-insulating and are effective to reduce the surface recombination velocity - diffusion length product by more than an order of magnitude.

Abstract: A surface oriented lateral bipolar transistor having a base of narrow width is fabricated by using a doped polycrystalline silicon layer as an ion implantation mask when implanting ions for the emitter and base regions. In forming the doped polysilicon mask, a first layer of dopant masking material is formed on the surface of a semiconductor substrate, a second layer of undoped polysilicon is formed over the first layer, and a third layer of dopant masking material is formed over the second layer. Portions of the second and third layers are removed and a dopant is diffused into the exposed edge portion of the second layer. The third layer and the undoped portion of the second layer are then removed thereby leaving only the doped portion of the second layer on the first layer.

Abstract: In forming p.sup.+ -type isolation region to define an isolated n-type island region in an n-type epitaxial layer grown on a p-type semiconductor substrate, the p.sup.+ -type isolation region is formed by burying, prior to the growing of the epitaxial layer, an Al-ion-implanted region in the p-type substrate by means of ion implantation and subsequent heat-treatment for driving-in, thereby enabling a very quick forming of the isolation region and an accurate control of the resistivity of the epitaxial layer.

Abstract: Cast and forged titanium alloys suited for use at temperatures over 600.degree. C. are based on TiAl gamma phase structure. Useful alloys have about 1.5% or greater tensile ductility at temperatures of 260.degree. C. and below, thereby making them fabricable and suited for engineering applications. Disclosed are alloys having weight percent compositions of 31-36 aluminum, 0-4 vanadium, balance titanium (in atomic percent, about: 45-50Al, 0-3V, bal Ti). The inclusion of about 0.1 weight percent carbon improves creep rupture strength. To obtain high tensile strength, the alloys are forged at about 1025.degree. C. and aged at about 900.degree. C.; to obtain higher creep rupture strength and tensile ductility, a solution anneal at about 1150.degree. C. is interposed before aging.

Abstract: A memory cell having two mesa bipolar transistors separated by a valley in which two doped polycrystalline load resistors are formed. Doped polycrystalline conductors connect the resistors to a respective backside metallic collector contact which is between a support structure and a transistor and to a respective base.The cell is fabricated by removing a substrate upon which was formed an epitaxial layer and top support, applying a backside metallic layer, forming a bottom support, removing the top support, etching the epitaxial layer to form mesas, etching the backside metal to form discrete contacts, and forming multi-level resistors and conductors in the valley between the mesa transistors separated by insulative material.

Abstract: A method for manufacturing semiconductor integrated circuits such as metal oxide semiconductor field effect transistors having source and drain regions to which contact holes are made such that not only the contact parts of the source and the drain regions, but also both surface parts of a field oxide layer which are adjacent to the outer edges of source and drain regions, are exposed and contacted.

Abstract: Titanium-aluminum-niobium alloys having narrow and critical composition ranges are disclosed. The alloys have room temperature tensile elongations of 1.5% or greater and creep strength to density ratios better than certain nickel superalloys. Thus, they may replace other heavier base alloys in many applications up to 750.degree. C. Aluminum content must be closely controlled as excess amount decreases ductility while insufficient amount decreases creep strength. Niobium content is also critical as excess amount adversely affects creep strength-to-density ratio while insufficient amount decreases ductility. And there is an important interrelationship between niobium and aluminum.Disclosed are alloys having atomic percent compositions of 24-27 Al, 11-16 Nb, balance Ti; more preferred are alloys of 24.5-26 Al, 12-15 Nb, balance Ti. (Nominally, these alloys in weight percent are Ti-13/15Al-19.5/30Nb and Ti-13.5/15Al-25/28Nb.

Abstract: A process for manufacturing a bipolar semiconductor device. An epitaxial layer is formed on a silicon wafer, and a base layer is formed by the diffusion of impurities having one conductivity type in a part of the epitaxial layer. Impurities having the opposite conductivity type are deposited in a part of the base layer, polycrystalline silicon is deposited on the entire surface of the wafer which is provided with windows for emitter, base and collector electrodes, and a gold-containing film is applied on the entire surface of the polycrystalline silicon layer. Impurities having the opposite conductivity type are deposited and driven into the base layer so as to form an emitter layer and simultaneously gold atoms are driven in through the collector windows into a collector layer of the epitaxial layer and through the base and emitter windows into the collector layer.

Abstract: A semiconductor structure is provided by forming an isolation region in a portion of a semiconductor layer, forming a doped region in the semiconductor layer adjacent the isolation region, such doped region having a conductivity type opposite the conductivity type of the semiconductor layer, selectively masking a surface of the semiconductor layer exposing a portion of the doped region adjacent to the isolation region, and selectively etching the exposed portions of the adjacent doped region forming a depression having converging side walls separated from the isolation region by portions of the doped region. The semiconductor layer is an epitaxial layer providing the collector region of a transistor. The bottom portion of the depression is lightly doped to provide an active base region for the transistor. The active base region is electrically connected to the base contact through the more heavily doped region formed in the semiconductor layer.

Abstract: Wafers of silicon semiconductor material are stacked, bonded and severed to form a plurality of semiconductor diodes. One or more capacitor bodies are physically and electrically joined with these diodes, either by means of the capacitor bodies themselves or by means of an intermediate lead frame structure, in order to facilitate the handling and processing of the assembly as a unit.

Abstract: A method for fabricating an MOS integrated circuit having a refractory metal gate structure includes the formation of an insulating layer and a conductive refractory metal layer on a substrate, followed by the selective removal of portions of these layers to define the locations of source, drain, and other diffused regions. After the diffusion or implantation of the drain and source regions, using the refractory metal as a mask, the refractory metal, other than at the gate regions, is removed, and the portion of the underlying insulating layer that is thereby exposed is then etched away. An oxidizing step is performed to form a thick oxide region at those areas of the substrate not covered by the remaining portions of the refractory metal layer. Also disclosed is an MOS refractory metal gate MOS device fabricated by the method.