Abstract: Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.

Abstract: A semiconductor device is provided. An insulating buried layer is formed in a substrate. Deep trench insulating structures are formed on the insulating buried layer. A deep trench contact structure is formed between the deep trench insulating structures. The deep trench contact structure is electrically connected with the substrate under the insulating buried layer.

Abstract: A modular, scalable focal plane array is provided as an array of integrated circuit dice, wherein each die includes a given amount of modular pixel array circuitry. The array of dice effectively multiplies the amount of modular pixel array circuitry to produce a larger pixel array without increasing die size. Desired pixel pitch across the enlarged pixel array is preserved by forming die stacks with each pixel array circuitry die stacked on a separate die that contains the corresponding signal processing circuitry. Techniques for die stack interconnections and die stack placement are implemented to ensure that the desired pixel pitch is preserved across the enlarged pixel array.

Abstract: A switching device includes a low voltage normally-off transistor and a control circuit built into a common die. The device includes source, gate and drain electrodes for the transistor and one or more auxiliary electrodes. The drain electrode is on one surface of a die on which the transistor is formed, while each of the remaining electrodes is located on an opposite surface. The one or more auxiliary electrodes provide electrical contact to the control circuit, which is electrically connected to one or more of the other electrodes.

Abstract: A multi-chip stack structure and a method for fabricating the same are provided.

Abstract: A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element.

Abstract: An embodiment of the invention discloses an optoelectronic semiconductor device. The optoelectronic semiconductor comprises a unit having a plurality of electrical connectors with top surfaces; an insulating material surrounding each of the plurality of electrical connectors, wherein each of the top surfaces are exposed through the insulating material; a semiconductor system, having a side surface directly covered by the insulation material, electrically connected to the plurality of electrical connectors and being narrower in width than both of the unit and the insulating material; an electrode formed on the semiconductor system at a position not corresponding to the plurality of electrical connectors; and a layer provided on the semiconductor system at a side opposite to the electrode and configured to laterally exceed outside more than one outermost boundary of the plurality of electrical connectors.

Abstract: A semiconductor light-emitting device includes a light-impervious substrate, a bonding structure, a semiconductor light-emitting stack, and a fluorescent material structure overlaying the semiconductor light-emitting stack. The semiconductor light-emitting stack is separated from a growth substrate and bonded to the light-impervious substrate via the bonding structure. A method for producing the semiconductor light-emitting device includes separating a semiconductor light-emitting stack from a growth substrate, bonding the semiconductor light-emitting stack to a light-impervious substrate, and forming a fluorescent material structure over the semiconductor light-emitting stack.

Abstract: An organic light-emitting diode includes an anode on a substrate; a first hole transporting layer on the anode; a second hole transporting layer on the first hole transporting layer and corresponding to the red and green pixel areas; a first emitting material pattern of a first thickness on the second hole transporting layer and corresponding to the red pixel area; a second emitting material pattern of a second thickness on the second hole transporting layer and corresponding to the green pixel area; a third emitting material pattern of a third thickness on the first hole transporting layer and corresponding to the blue pixel area; an electron transporting layer on the first, second and third emitting material patterns; and a cathode on the electron transporting layer, wherein the second thickness is less than the first thickness and greater than the third thickness.

Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.

Abstract: A power device (such as a power diode) has a peripheral die area and a central area. The main PN junction of the device is formed by a P+ type region that extends down into an N? type layer. The central portion of the P+ type region has a plurality of openings so mesa structures of the underlying N? type material extend up to the semiconductor surface through the openings. Due to the mesa structures being located in the central portion of the die, there are vertically extending extensions of the PN junction in the central portion of the die. Minority carrier charge storage is more uniform per unit area across the surface of the die. Due to the form of the P+ type region and the mesa structures, the reverse recovery of the PN junction exhibits a soft characteristic.

Abstract: The present disclosure provides a buried channel semiconductor structure in which a crystallographic wet etch is used to tailor the profile of etched regions formed into a multilayered substrate which includes a compound semiconductor layer located atop a buried semiconductor channel material layer. The use of crystallographic wet etching on a compound semiconductor allows one to tailor the shape of a source recess region and a drain recess region formed into a multilayered substrate. This allows for the control of gate overlap/underlap. Also, the use of crystallographic wet etching on a compound semiconductor allows independent control of the length of an underlying buried semiconductor channel region.

Abstract: A solid-state image pickup device has photodiodes, each of which includes an N-type region formed in a semiconductor substrate, a first silicon carbide layer formed above the N-type region, and a P-type region including a first silicon layer formed above the first silicon carbide layer and doped with boron. A fabrication process of such a solid-state image pickup device is also disclosed.

Abstract: A method of assembling a semiconductor chip device is provided that includes providing a circuit board including a surface with an aperture. A portion of a first heat spreader is positioned in the aperture. A stack is positioned on the first heat spreader. The stack includes a first semiconductor chip positioned on the first heat spreader and a substrate that has a first side coupled to the first semiconductor chip.

Abstract: A low leakage, low capacitance diode based triggered electrostatic discharge (ESD) silicon controlled rectifiers (SCR), methods of manufacture and design structure are provided. The method includes providing a silicon film on an insulator layer. The method further includes forming isolation regions which extend from an upper side of the silicon layer to the insulator layer. The method further includes forming one or more diodes in the silicon layer, including a p+ region and an n+ region formed in a well bordered by the isolation regions. The isolation regions isolate the one or more diodes in a vertical direction and the insulator layer isolates the one or more diodes from an underlying P or N type substrate, in a horizontal direction.

Abstract: The leakage current generated in a pn junction region between a gate and a source is reduced in a junction FET using a silicon carbide substrate. In a trench junction FET using a silicon carbide substrate, nitrogen is introduced into a sidewall and a bottom surface of a trench, thereby forming an n type layer and an n+ type layer on a surface of the trench. In this manner, the pn junction region corresponding to the junction region between a p+ type gate region and an n+ type source region is exposed on a main surface of a semiconductor substrate instead of on the damaged sidewall of the trench, and also the exposed region thereof is narrowed. Accordingly, the leakage current in the pn junction region can be reduced.

Abstract: To provide a light emitting device that makes it possible to form a surface light emitting apparatus of less unevenness in luminance. The light emitting device 10 of the present invention comprises a light emitting element 30, connecting terminals 21a, 21b connected with the light emitting element 30, a package 12 which has a recess 40 wherein the light emitting element 30 is mounted and from which a part of each connecting terminal 21a, 21b is projected outward, an opening 41 of the recess 40 being elongated in one direction, wherein both side walls of the recess 40 positioned in the longitudinal direction of the recess 40 are inclined surface 43, an angle ? between both the inclined surfaces 43 being 90 degrees or more. In the light emitting device 10 of the present invention, light emitted by the light emitting element 30 is spread sufficiently in the longitudinal direction of the opening 41 so as to produce a band-shaped beam.

Abstract: A lateral power semiconductor component has a front side, a rear side and a lateral edge. The component further includes a drift zone of a first conductivity type, a source zone of the first conductivity type, a body zone of a second conductivity type opposite the first conductivity type, and a drain zone of the first conductivity type. A gate forms a MOS structure with the drift zone, the source zone and the body zone. A horizontally extending field plate above each semiconductor region of the power semiconductor component forms a plate capacitor structure with an edge plate lying under the field plate. The edge plate includes a highly doped semiconductor material and is electrically connected to one of a source potential and a drain potential of the power semiconductor component.

Abstract: A semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump. The bump is connected to the line and is adapted to be electrically connected to the line. A plane that is horizontal to an active surface of the semiconductor chip is defined. The area that the connection region of the line and the bump is projected on the plane is larger than 30,000 square microns or has an extension distance larger than 500 microns.

Abstract: Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines.