Patents Examined by Wael M. Fahmy
  • Patent number: 10332871
    Abstract: Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 25, 2019
    Assignee: Intel IP Corporation
    Inventors: Christian Cornelius Russ, Giuseppe Curello, Tomasz Biedrzycki, Franz Kuttner, Luis F. Giles, Bernhard Stein
  • Patent number: 10332934
    Abstract: Some embodiments include a memory array which has a first series of access/sense lines extending along a first direction, and a second series of access/sense lines over the first series of access/sense lines and extending along a second direction which crosses the first direction. Memory cells are vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. Resistance-increasing material is adjacent to and coextensive with the access/sense lines of one of the first and second series, and is between the adjacent access/sense lines and programmable material of the memory cells. Some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Lindenberg
  • Patent number: 10325855
    Abstract: A device and method of fabricating are provided. The device includes a substrate having a first side and an opposite second side, a cavity defined within the substrate from the first side, a die coupled to a floor of the cavity and having a conductive pad on a side of the die distal to the floor of the cavity. A laminate layer coupled to the second side of the substrate may be included. A hole may be drilled, at one time, through layers of the device, through the die, and through the conductive pad. The hole extends through and is defined within the laminate layer (if present), the second side of the substrate, the die, and the conductive pad. A conductive material is provided within the hole and extends between and through the laminate layer (if provided), the second side of the substrate, the die, and the conductive pad.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Kim, Jie Fu, Changhan Yun, Chin-Kwan Kim, Manuel Aldrete, Chengjie Zuo, Mario Velez, Jonghae Kim
  • Patent number: 10326059
    Abstract: A light emitting device can include a light emitting structure including a p-GaN based layer, an active layer having multiple quantum wells, and an n-GaN based layer; a p-electrode and an n-electrode electrically connecting with the light emitting structure, respectively, in which the n-electrode has a plurality of layers; a phosphor layer disposed on a top surface of the light emitting structure; and a passivation layer disposed between the phosphor layer and the top surface of the light emitting structure, and disposed on outermost side surfaces of the light emitting structure, in which the p-electrode and the n-electrode are disposed on opposite sides of the light emitting structure. Also, the phosphor layer has a two-digit micrometer thickness, and includes a pattern to bond an n-electrode pad on a portion of the n-electrode by a wire, and comprises different phosphor materials configured to emit light of different colors.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: June 18, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Myung Cheol Yoo
  • Patent number: 10325782
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 18, 2019
    Assignee: UTAC Headquarters PTE. Ltd.
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Patent number: 10319710
    Abstract: Provided is a semiconductor device with a reduced variation in temperature among a plurality of unit transistors. A semiconductor device includes: a semiconductor substrate; and a transistor group including at least one column in which a plurality of unit transistors are aligned and arranged along a first axis on the semiconductor substrate. A first column of the at least one column includes: a first group of transistors including two of the unit transistors that are adjacent to each other with a first distance therebetween, and a second group of transistors including two of the unit transistors that are adjacent to each other with a second distance therebetween, the first group of transistors is disposed at a position closer to a center of the first column along the first axis than the second group of transistors, and the first distance is larger than the second distance.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 11, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuri Honda, Fumio Harima, Kazuhito Nakai
  • Patent number: 10319834
    Abstract: Methods of forming an EDNMOS with polysilicon fingers between a gate and a nitride spacer and the resulting devices are provided. Embodiments include forming a polysilicon layer upon a GOX layer over a substrate; forming a gate and plurality of fingers and a gate and plurality of fingers through the polysilicon layer down the GOX layer; forming an oxide layer over the GOX layer and sidewalls of the gates and fingers; forming a nitride layer over the oxide layer; removing portions of the nitride and oxide layers down to the polysilicon and GOX layers to form nitride spacers; and forming S/D regions laterally separated in the substrate, each S/D region adjacent to a nitride spacer.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: June 11, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lin Wei, Upinder Singh, Raj Verma Purakh
  • Patent number: 10319822
    Abstract: This method for controlling an IGBT-type transistor includes a phase for switching the transistor between an on state and an off state. Said phase comprises generating a setpoint current whereof the intensity on the gate of the transistor assumes different setpoint values. At least some of the setpoint values are chosen as a function of the sign of the temporal derivative of the main current. Each setpoint value is chosen from a set of predetermined setpoint values.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: June 11, 2019
    Assignee: ALSTOM TRANSPORT TECHNOLOGIES
    Inventors: Florent Andrianoelison, Eric Rabasse, Stephane Boisteau
  • Patent number: 10304839
    Abstract: A metal strap is formed in a middle-of-line (MOL) process for communication between an eDRAM and a FinFET. An oxide is deposited in a trench over the eDRAM to prevent development of an epitaxial film prior to formation of the metal strap. The result is an epiless eDRAM strap in a FinFET.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10290816
    Abstract: An organic light emitting device is disclosed whose emissive layer has a host material, a first emissive dopant, and a second dopant. The second dopant is an excited energy state managing dopant provided in an amount between 2-10 vol. % of the emissive layer and has a lowest triplet state energy level, TM, that is higher than a lowest triplet state energy levels, T1, of both the host and the first dopant and lower than the multiply-excited energy level, T*, of the first dopant.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: May 14, 2019
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Stephen R. Forrest, Jaesang Lee, Quinn Burlingame
  • Patent number: 10262959
    Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: April 16, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Evelyn Napetschnig, Ulrike Fastner, Alexander Heinrich, Thomas Fischer
  • Patent number: 10256169
    Abstract: A highly-reliable semiconductor device has improved adhesion between a sealing material and a sealed metal member and/or a case member. In some implementations, the semiconductor device includes: a laminated substrate on which a semiconductor element is mounted; and a sealing material. In some implementations, the sealing material contains an epoxy base resin, a curing agent, and a phosphonic acid.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 9, 2019
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Naoyuki Kanai, Tatsuhiko Asai
  • Patent number: 10224254
    Abstract: A package structure may include a one-piece metal carrier, a die, a mold layer and a redistribution layer. The one-piece metal carrier may include a bottom portion and a first supporting structure, and the one-piece metal carrier may have a recess defined by the bottom portion and the first supporting structure. The die may be disposed in the recess of the one-piece metal carrier, and the die may have a plurality of conductive bumps. The mold layer may be formed to encapsulate the die. The mold layer may expose a portion of each of the plurality of conductive bumps and a portion of the first supporting structure. The redistribution layer may be disposed on the mold layer and electrically connected to the plurality of conductive bumps.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: March 5, 2019
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventors: Ming-Chih Chen, Hsien-Wen Hsu, Yuan-Fu Lan, Hung-Hsin Hsu
  • Patent number: 10217810
    Abstract: The teachings of the present disclosure may be applied to the manufacture and design of capacitors. In some embodiments of these teachings, a capacitor may be formed on a heavily doped substrate. For example, a method for manufacturing a capacitor may include: depositing an oxide layer on a first side of a heavily doped substrate; depositing a first metal layer on the oxide layer; and depositing a second metal layer on a second side of the heavily doped substrate.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: February 26, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Greg Dix, Randy Yach, Francesco Mazzilli
  • Patent number: 10204981
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a first dielectric layer, a first doping layer of a first conductivity type, and a second doping layer of a second conductivity type. The substrate has a fin portion. The first dielectric layer is disposed on the substrate and surrounds the fin portion. The first doping layer of the first conductivity type is disposed on the first dielectric layer and is located on two opposite sidewalls of the fin portion. The second doping layer of the second conductivity type is disposed on the two opposite sidewalls of the fin portion and is located between the fin portion and the first doping layer. The first doping layer covers a sidewall and a bottom surface of the second doping layer.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: February 12, 2019
    Assignee: United Microelectronics Corp.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Ching-Ling Lin
  • Patent number: 9553047
    Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the patterning of the array and periphery regions in self-aligned quadruple patterning and provide semiconductor devices resulting from the combined patterning.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: January 24, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Min Hung, Tzung-Ting Han, Miao-Chih Hsu
  • Patent number: 8471283
    Abstract: A white LED lamp including: a conductive portion; a light emitting diode chip mounted on the conductive portion, for emitting a primary light having a peak wavelength of 360 nm to 420 nm; a transparent resin layer including a first hardened transparent resin, for sealing the light emitting diode chip; and a phosphor layer covering the transparent resin layer, the phosphor layer being formed by dispersing a phosphor powder into a second hardened transparent resin, and the phosphor powder receiving the primary light and radiating a secondary light having a wavelength longer than that of the primary light. An energy of the primary light contained in the radiated secondary light is 0.4 mW/lm or less. In the white LED lamp, a backlight, and an illumination device using the white LED lamp an amount of UV light to be contained in the released light and an amount of heat to be generated from the lamp are decreased to be small.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: June 25, 2013
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Materials Co., Ltd.
    Inventors: Tsutomu Ishii, Hajime Takeuchi, Yasumasa Ooya, Katsutoshi Nakagawa, Yumi Ito, Masaki Toyoshima, Yasuhiro Shirakawa, Ryo Sakai
  • Patent number: 8338822
    Abstract: An electrical connection structure having elongated carbon structures electrically connected to an electroconductive body is obtained by successively layering an electroconductive catalyst support layer, a fine catalyst particle layer for producing the elongated carbon structures and the elongated carbon structures on the electroconductive body. A low-resistance electrical connection structure is provided.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: December 25, 2012
    Assignee: Fujitsu Limited
    Inventor: Shintaro Sato
  • Patent number: 8067837
    Abstract: A semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump. The bump is connected to the line and is adapted to be electrically connected to the line. A plane that is horizontal to an active surface of the semiconductor chip is defined. The area that the connection region of the line and the bump is projected on the plane is larger than 30,000 square microns or has an extension distance larger than 500 microns.
    Type: Grant
    Filed: June 17, 2005
    Date of Patent: November 29, 2011
    Assignee: Megica Corporation
    Inventor: Mou-Shiung Lin
  • Patent number: 8030125
    Abstract: The present invention is a method for manufacturing an organic thin-film transistor substrate including an organic thin-film transistor as a transistor element, and an object of the invention is to provide a manufacturing method capable of forming a bank in a smaller number of steps.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: October 4, 2011
    Assignee: Sumitomo Chemical Company, Limited
    Inventor: Kenji Kasahara