Patents Examined by Wael M. Fahmy
  • Patent number: 8030195
    Abstract: An object of the invention is to provide a TFT substrate and a method for producing a TFT substrate which is capable of drastically reducing the production cost by decreasing the number of steps in the production process and improving production yield. A TFT substrate includes: a substrate; a gate electrode and a gate wire formed above the substrate; a gate insulating film formed above the gate electrode and the gate wire; a first oxide layer formed above the gate insulating film which is formed at least above the gate electrode; and a second oxide layer formed above the first oxide layer; wherein at least a pixel electrode is formed from the second oxide layer.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: October 4, 2011
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Kazuyoshi Inoue, Koki Yano, Nobuo Tanaka, Tokie Tanaka, legal representative
  • Patent number: 8026611
    Abstract: A microelectronic assembly including a first and second microelectronic elements. Each of the microelectronic elements have oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: September 27, 2011
    Assignee: Tessera, Inc.
    Inventors: Ilyas Mohammed, Belgacem Haba
  • Patent number: 8021908
    Abstract: A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a second polarity voltage on the gate of a transfer transistor during a charge integration period.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: September 20, 2011
    Assignee: Micron Technology, Inc.
    Inventor: John Ladd
  • Patent number: 8022421
    Abstract: A method for forming a pixel of an LED light source is provided. The method includes following steps: forming a first layer on a substrate; forming a second layer and a first light-emitting active layer on the first layer; exposing a portion of an upper surface of the first layer; forming a third layer on the substrate; forming a fourth layer and a second light-emitting active layer on the third layer; exposing a portion of an upper surface of the third layer; and forming a first electrode on the exposed upper surface of the first layer, a second electrode on a portion of an upper surface of the second layer, a third electrode on the exposed upper surface of the third layer, and a fourth electrode a portion of an upper surface of the fourth layer. The first light-emitting active layer and the second light-emitting active layer emit different colors of light.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: September 20, 2011
    Assignee: Industrial Technology Institute
    Inventors: Han-Tsung Hsueh, Hsi-Hsuan Yen, Wen-Yung Yeh, Mu-Tao Chu
  • Patent number: 8017968
    Abstract: A light-emitting diode chip package body with an excellent heat dissipation performance and a low manufacturing cost, and a packaging method of the same are disclosed. A LED chip package body is provided, the LED chip package body comprising: a LED chip having an electrode-side surface and at least two electrodes mounted on said electrode-side surface; an electrode-side insulating layer formed on said electrode-side surface of said LED chip and formed with a plurality of through-holes registered with corresponding said electrodes; a highly heat-dissipating layer formed in each of said through-holes of said insulating layer on said electrode-side surface; and a highly heat-conducting metal layer formed on said highly heat-dissipating layer in each of said through-holes.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: September 13, 2011
    Inventor: Yu-Nung Shen
  • Patent number: 8017986
    Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: September 13, 2011
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Toshihiro Tanaka, Yukiko Umemoto, Mitsuru Hiraki, Yutaka Shinagawa, Masamichi Fujito, Kazufumi Suzukawa, Hiroyuki Tanikawa, Takashi Yamaki, Yoshiaki Kamigaki, Shinichi Minami, Kozo Katayama, Nozomu Matsuzaki
  • Patent number: 8008165
    Abstract: Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: August 30, 2011
    Assignees: Sumitomo Electric Industries, Ltd., Sony Corporation
    Inventors: Masahiro Nakayama, Naoki Matsumoto, Koshi Tamamura, Masao Ikeda
  • Patent number: 8008739
    Abstract: A microelectromechanical apparatus (X) includes a microelectromechanical component (10), an insulating substrate (21), a through via (22c) disposed in the insulating substrate (21), a sealing member (30) and a conductive connecting member (40). The microelectromechanical device (10) has a semiconductor substrate (11), a microelectromechanical system (12) and an electrode (13) electrically connected to the microelectromechanical system (12). The sealing member (30) is made of glass, is disposed so as to enclose the microelectromechanical system (12) between the semiconductor substrate (11) and the insulating substrate (21), and hermetically seals the microelectromechanical system (12). The conductive connecting member (40) electrically connects the electrode (13) and an end of the through via (22c), at a position spaced away from the sealing member (30).
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: August 30, 2011
    Assignee: Kyocera Corporation
    Inventor: Itaru Ishii
  • Patent number: 8003977
    Abstract: It is an object of the present invention to provide a light emitting element with improved luminous efficiency, a reduced drive voltage, and improved degree of deterioration with respect to driving time. According to a light emitting element including a first electrode; a second electrode; and a light emitting laminated body formed therebetween, the light emitting laminated body has at least a first layer, a second layer, and a third layer in this order, the first layer is a layer having a carrier transporting property, the third layer is a layer including an emission center material and a host material in which the emission center material is dispersed, the second layer has an energy gap larger than that of the first layer and equal to or larger than that of the host material, and the second layer has a thickness of 0.1 nm or more and less than 5 nm.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: August 23, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Nobuharu Ohsawa, Yuji Iwaki, Satoshi Seo
  • Patent number: 8003981
    Abstract: The present invention provides a field effect transistor including an oxide film as a semiconductor layer, wherein the oxide film includes one of a source part and a drain part to which one of hydrogen and deuterium is added.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: August 23, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tatsuya Iwasaki, Hideya Kumomi
  • Patent number: 8003417
    Abstract: A method of manufacturing an organic electroluminescent display device may comprise forming transistors on a substrate, forming a lower electrode over an insulating layer, forming an insulating layer on the transistors, the lower electrode being coupled to a source or a drain of each of the transistors, forming a bank layer on the lower electrode, the bank layer having openings to expose part of the lower electrode, forming a bus electrode on the bank layer, forming an organic light-emitting layer to cover the lower electrode, the bank layer, and the bus electrode, patterning the organic light-emitting layer using a laser, thereby exposing the bus electrode placed on the bank layer, and forming an upper electrode on the organic light-emitting layer so that the upper electrode comes into contact with the exposed bus electrode.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: August 23, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Fengjin Li, Jaeyoung Lee, Taeyeon Yoo
  • Patent number: 8003976
    Abstract: An organic light-light conversion device excellent in device characteristics, comprising a light sensing unit having a layer including a photo-conductive organic semiconductor developing a photo-current multiplication phenomenon by light irradiation, and a light emitting unit having a layer including an electroluminescent organic semiconductor emitting light by current injection, characterized in that at least one of the photo-conductive organic semiconductor and an electroluminescent organic semiconductor is polymer semiconductor. An imaging intensifier consisting of a plurality of arranged above organic light-light conversion devices. An optical sensor provided with a means of measuring and outputting voltages applied to the above organic light-light conversion device and to the opposite ends of a layer including the electroluminescent organic semiconductor.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: August 23, 2011
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kenichi Nakayama, Masaaki Yokoyama, Masato Ueda
  • Patent number: 8003447
    Abstract: A multi-chip module suitable for use in a battery protection circuit. The multi-chip module includes an integrated circuit chip, a first power transistor, a second power transistor, a first connection structure electrically coupling the integrated circuit chip to the first power transistor, a second connection structure electrically coupling the integrated circuit chip to the second power transistor, and a leadframe structure comprising a first lead, a second lead, a third lead and a fourth lead, wherein the integrated circuit chip, the first power transistor, and the second power transistor are mounted on the leadframe structure. A molding material covers at least part of the integrated circuit chip, the first power transistor, the second power transistor, the first connection structure, and the second connection structure.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: August 23, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jeongil Lee, Myoungho Lee, Bigildis Dosdos, Charles Suico, Edwin Man Fai Lee, David Chong Sook Lim, Adriano M. Vilas-Boas
  • Patent number: 8004089
    Abstract: On the lower surface of a semiconductor construct having an external connection electrode, there are formed an insulating film having a planar size greater than that of the semiconductor construct, and a metal layer and a mask metal layer having a connection pad portion in which a first opening corresponding to the external connection electrode is formed. A laser beam is applied using the mask metal layer as a mask, and a second opening is thereby formed in a part of the insulating film corresponding to the external connection electrode. Then, a connection conductor is formed to connect a wiring line to the external connection electrode via the second opening of the insulating film.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: August 23, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hiroyasu Jobetto
  • Patent number: 7999299
    Abstract: Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second node is electrically connected to a plurality of upper electrodes of the capacitors in the peripheral circuit region to connect at least a portion of the capacitors in parallel. The first node is formed at substantially the same level as a bit line in a cell array region and is formed of the same material used to form the bit line.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: August 16, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hwa Lee, Si-Woo Lee
  • Patent number: 7999270
    Abstract: The present invention discloses a III-nitride compound semiconductor light emitting device having an n-type nitride compound semiconductor layer, an active layer grown on the n-type nitride compound semiconductor layer, for generating light by recombination of electron and hole, and a p-type nitride compound semiconductor layer grown on the active layer. The III-nitride compound semiconductor light emitting device includes a plurality of semiconductor layers including a nitride compound semiconductor layer with a pinhole structure grown on the p-type nitride compound semiconductor layer.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: August 16, 2011
    Assignee: Epivalley Co., Ltd.
    Inventors: Eun Hyun Park, Tae-Kyung Yoo
  • Patent number: 7999317
    Abstract: A p-type body region and an n-type buffer region are formed on an n? drift region. An n++ emitter region and a p++ contact region are formed on the p-type body region in contact with each other. A p++ collector region is formed on the n-type buffer region. An insulating film is formed on the n? drift region, and a gate insulating film is formed on the n++ emitter region, the p-type body region, and the n drift region. A gate electrode is formed on the insulating film and the gate insulating film. A p+ low-resistivity region is formed in the p-type body region and surrounding the interface between the n++ emitter region and between the p-type body region and the p++ contact region. The p-type body region has two local maxima of an impurity concentration profile at the interface between the body region and the gate insulating film.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: August 16, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Hong-Fei Lu, Mizushima Tomonori
  • Patent number: 7999313
    Abstract: A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: August 16, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyung Do Kim
  • Patent number: 7998884
    Abstract: A light emitting device using a silicon (Si) nanocrystalline Si insulating film is presented with an associated fabrication method. The method provides a doped semiconductor or metal bottom electrode. Using a high density plasma-enhanced chemical vapor deposition (HDPECVD) process, a Si insulator film is deposited overlying the semiconductor electrode, having a thickness in a range of 30 to 200 nanometers (nm). For example, the film may be SiOx, where X is less than 2, Si3Nx, where X is less than 4, or SiCx, where X is less than 1. The Si insulating film is annealed, and as a result, Si nanocrystals are formed in the film. Then, a transparent metal electrode is formed overlying the Si insulator film. An annealed Si nanocrystalline SiOx film has a turn-on voltage of less than 20 volts, as defined with respect to a surface emission power of greater than 0.03 watt per square meter.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: August 16, 2011
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jiandong Huang, Pooran Chandra Joshi, Apostolos T. Voutsas, Hao Zhang
  • Patent number: 7998791
    Abstract: Panel level methods and arrangements are described for attaching heat sinks in panel form with dice attached to a leadframe panel. Various methods produce integrated circuit packages each having an exposed heat sink on one outer surface of the package and an exposed die attach pad on a second opposite surface of the package.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: August 16, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Sek Hoi Chong, Shee Min Yeong, Danny Cher Hau Koh, Eugene Kai Poh Wong