Abstract: A p-type body region and an n-type buffer region are formed on an n? drift region. An n++ emitter region and a p++ contact region are formed on the p-type body region in contact with each other. A p++ collector region is formed on the n-type buffer region. An insulating film is formed on the n? drift region, and a gate insulating film is formed on the n++ emitter region, the p-type body region, and the n drift region. A gate electrode is formed on the insulating film and the gate insulating film. A p+ low-resistivity region is formed in the p-type body region and surrounding the interface between the n++ emitter region and between the p-type body region and the p++ contact region. The p-type body region has two local maxima of an impurity concentration profile at the interface between the body region and the gate insulating film.
Abstract: A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another.
Abstract: A light emitting device using a silicon (Si) nanocrystalline Si insulating film is presented with an associated fabrication method. The method provides a doped semiconductor or metal bottom electrode. Using a high density plasma-enhanced chemical vapor deposition (HDPECVD) process, a Si insulator film is deposited overlying the semiconductor electrode, having a thickness in a range of 30 to 200 nanometers (nm). For example, the film may be SiOx, where X is less than 2, Si3Nx, where X is less than 4, or SiCx, where X is less than 1. The Si insulating film is annealed, and as a result, Si nanocrystals are formed in the film. Then, a transparent metal electrode is formed overlying the Si insulator film. An annealed Si nanocrystalline SiOx film has a turn-on voltage of less than 20 volts, as defined with respect to a surface emission power of greater than 0.03 watt per square meter.
Abstract: Panel level methods and arrangements are described for attaching heat sinks in panel form with dice attached to a leadframe panel. Various methods produce integrated circuit packages each having an exposed heat sink on one outer surface of the package and an exposed die attach pad on a second opposite surface of the package.
February 1, 2008
Date of Patent:
August 16, 2011
National Semiconductor Corporation
Sek Hoi Chong, Shee Min Yeong, Danny Cher Hau Koh, Eugene Kai Poh Wong
Abstract: A lead frame (100) for a semiconductor device is formed by applying nickel plating (102), palladium plating (103), and gold flash plating (104) substantially entirely to lead frame body (101) such as copper thin plate in this order, and further applying silver plating (105) selectively to part of an inner part that is to be enclosed with a package of the semiconductor device. The lead frame (100) may also include a base of the package. The silver plating contributes to an excellent light reflectance and wire bonding efficiency of the inner part, whereas the gold flash plating contributes to an excellent resistance to corrosion and soldering efficiency of an outer part that is outside the package.
Abstract: A semiconductor device according to an aspect of the invention comprises an n-type FinFET which is provided on a semiconductor substrate and which includes a first fin, a first gate electrode crossing a channel region of the first fin via a gate insulating film in three dimensions, and contact regions provided at both end of the first fin, a p-type FinFET which is provided on the semiconductor substrate and which includes a second fin, a second gate electrode crossing a channel region of the second fin via a gate insulating film in three dimensions, and contact regions provided at both end of the second fin, wherein the n- and the p-type FinFET constitute an inverter circuit, and the fin width of the contact region of the p-type FinFET is greater than the fin width of the channel region of the n-type FinFET.
Abstract: According to one embodiment, a power transistor package includes an electrically conductive flange configured to be connected to a source of a power transistor device. The package further includes a first terminal mechanically fastened to the flange and configured to be electrically connected to a gate of the power transistor device and a second terminal mechanically fastened to the flange and configured to be electrically connected to a drain of the power transistor device. The package also includes a bus bar mechanically fastened to the flange which extends between and connects at least two different DC bias terminals mechanically fastened to the flange. The bus bar is configured to be electrically connected to the drain via one or more RF grounded connections.
Abstract: A spin injection device capable of spin injection magnetization reversal at low current density, a magnetic apparatus using the same, and magnetic thin film using the same, whereby the spin injection device (14) including a spin injection part (1) comprising a spin polarization part (9) including a ferromagnetic fixed layer (26) and an injection junction part (7) of nonmagnetic layer, and a ferromagnetic free layer (27) provided in contact with the spin injection part (1) is such that in which the nonmagnetic layer (7) is made of either an insulator (12) or a conductor (25), a nonmagnetic layer (28) is provided on the surface of the ferromagnetic free layer (27), electric current is flown in the direction perpendicular to the film surface of the spin injection device (14), and the magnetization of the ferromagnetic free layer (27) is reversed. This is applicable to such various magnetic apparatuses and magnetic memory devices as super gigabit large capacity, high speed, non-volatile MRAM and the like.
Abstract: A method produces a vertical field-effect transistor having a semiconductor layer, in which a doped channel region is arranged along a depression. A “buried” terminal region leads as far as a surface of the semiconductor layer. The field-effect transistor also has a doped terminal region near an opening of the depression as well as the doped terminal region remote from the opening, a control region arranged in the depression, and an electrical insulating region between the control region and the channel region. The terminal region remote from the opening leads as far as a surface containing the opening or is electrically conductively connected to an electrically conductive connection leading to the surface. The control region is arranged in only one depression. The field-effect transistor is a drive transistor at a word line or at a bit line of a memory cell array.
Abstract: A method of realizing a flash floating poly gate using an MPS process can include forming a tunnel oxide layer on an active region of a semiconductor substrate; and then forming a first floating gate on and contacting the tunnel oxide layer; and then forming second and third floating gates on and contacting the first floating gate, wherein the second and third floating gates extend perpendicular to the first floating gate; and then forming a poly meta-stable polysilicon layer on the first, second and third floating gates; and then forming a control gate on the semiconductor substrate including the poly meta-stable polysilicon layer. Therefore, it is possible to increase the surface area of the capacitor by a limited area in comparison with a flat floating gate. As a result, it is possible to improve the coupling ratio essential to the flash memory device and to improve the yield and reliability of the semiconductor device.
Abstract: A field-effect transistor including an electrically conductive substrate; a first insulating film coating the electrically conductive substrate; a gate electrode disposed on the electrically conductive substrate with the first insulating film interposed therebetween; a source electrode; a drain electrode opposing the source electrode with the channel therebetween; a second insulating film covering the gate electrode; and a semiconductor layer having a width larger than a width of the gate electrode in the channel width direction and being partly provided on the gate electrode with the second insulating film interposed therebetween so that the gate electrode, the second insulating film, and the semiconductor layer are laminated in the channel.
Abstract: Vertical field effect transistor semiconductor structures and methods for fabrication of the vertical field effect transistor semiconductor structures provide an array of semiconductor pillars. Each vertical portion of each semiconductor pillar in the array of semiconductor pillars has a linewidth greater than a separation distance to an adjacent semiconductor pillar. Alternatively, the array may comprise semiconductor pillars with different linewidths, optionally within the context of the foregoing linewidth and separation distance limitations. A method for fabricating the array of semiconductor pillars uses a minimally photolithographically dimensioned pillar mask layer that is annularly augmented with at least one spacer layer prior to being used as an etch mask.
August 14, 2009
Date of Patent:
July 19, 2011
International Business Machines Corporation
Matthew J. Breitwisch, Chung H. Lam, Alejandro G. Schrott
Abstract: A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.
Abstract: A semiconductor substrate includes a silicon carbide substrate having a first impurity concentration, a first silicon carbide layer formed on the silicon carbide substrate and having a second impurity concentration, and a second silicon carbide layer of a first conductivity type formed on the first silicon carbide layer and having a third impurity concentration, wherein the second impurity concentration is higher the an either the first impurity concentration or the third impurity concentration.
Abstract: An inductor includes an inductor wiring made of a metal layer and having a spiral planar shape. In a cross-sectional shape in a width direction of the inductor wiring, the inductor wiring has a larger film thickness at least in its inner side end than in its middle part.
Abstract: To provide a semiconductor layer in which a GaN system epitaxial layer having high crystal quality can be obtained. The semiconductor layer includes a ?-Ga2O3 substrate 1 made of a ?-Ga2O3 single crystal, a GaN layer 2 formed by subjecting a surface of the ?-Ga2O3 substrate 1 to nitriding processing, and a GaN growth layer 3 formed on the GaN layer 2 through epitaxial growth by utilizing an MOCVD method. Since lattice constants of the GaN layer 2 and the GaN growth layer 3 match each other, and the GaN growth layer 3 grows so as to succeed to high crystalline of the GaN layer 2, the GaN growth layer 3 having high crystalline is obtained.
Abstract: A semiconductor wafer may include, but is not limited to, the following elements. A semiconductor substrate has a device region and a dicing region. A stack of inter-layer insulators may extend over the device region and the dicing region. Multi-level interconnections may be disposed in the stack of inter-layer insulators. The multi-level interconnections may extend in the device region. An electrode layer may be disposed over the stack of inter-layer insulators. The electrode layer may extend in the device region. The electrode layer may cover the multi-level interconnections. A cracking stopper groove may be disposed in the dicing region. The cracking stopper groove may be positioned outside the device region.
Abstract: A field plate portion (5) overhanging a drain side in a visored shape is formed in a gate electrode (2). A multilayered film including a SiN film (21) and a SiO2 film (22) is formed beneath the field plate portion (5). The SiN film (21) is formed so that a surface of an AlGaN electron supply layer (13) is covered therewith.
Abstract: A method for manufacturing a semiconductor device includes forming an ONO layer in a memory region and forming several gate oxide layer patterns in a logic region, a nitride layer in the logic region can be used as a hard mask, enabling a reduction in the number of masks used. This results in improved manufacturing efficiency and reduced manufacturing costs of a SONOS semiconductor device.
Abstract: An object of the present invention is to provide a small solid-state image sensor which realizes significant improvement in sensitivity. The solid-state image sensor of the present invention includes a semiconductor substrate in which photoelectric conversion units are formed, a light-blocking film which is formed above the semiconductor substrate and has apertures formed so as to be positioned above respective photoelectric conversion units, and a high refractive index layer formed in the apertures. Here, each aperture has a smaller aperture width than a maximum wavelength in a wavelength of light in a vacuum converted from a wavelength of the light entering the photoelectric conversion unit through the apertures, and the high refractive index is made of a high refractive index material having a refractive index which allows transmission of light having the maximum wavelength through the aperture.