Patents Examined by Wael M. Fahmy
  • Patent number: 7906813
    Abstract: A semiconductor device, includes: a semiconductor layer, arranged, via an insulation layer, on a region of a part of a semiconductor substrate; a first circuit block formed on the semiconductor layer; and a second and a third circuit blocks formed on the semiconductor substrate, isolated from each other by the first circuit block.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: March 15, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Juri Kato
  • Patent number: 7906827
    Abstract: A solid-state imaging device includes a first wiring layer, a second wiring layer, a substrate contact, and a first contact. The arrangement of the substrate contact with respect to a light-receiving section forming a peripheral pixel is shifted, or not shifted, from the arrangement of the substrate contact with respect to a light-receiving section forming a central pixel, by a shift amount r from the peripheral portion toward the central portion. The arrangement of the first contact with respect to the light-receiving section of the peripheral pixel is shifted from the arrangement of the first contact with respect to the light-receiving section of the central pixel, by a shift amount s1 from the peripheral portion toward the central portion. The shift amount s1 is greater than the shift amount r.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: March 15, 2011
    Assignee: Panasonic Corporation
    Inventors: Motonari Katsuno, Ryohei Miyagawa, Hirohisa Ohtsuki
  • Patent number: 7902579
    Abstract: A magnetic memory device includes a memory region, an input and a sensor. The memory region includes a free layer, a pinned layer and a non-magnetic layer. The free layer has adjacent sectors and a magnetic domain wall. The pinned layer corresponds to the sectors and has a fixed magnetization direction. The non-magnetic layer is formed between the free layer and the pinned layer. The memory region includes a magnetic domain wall stopper for stopping the magnetic domain wall formed at each boundary of the sectors. The input is electrically connected to one end of the free layer for inputting a signal for magnetic domain dragging. The sensor measures a current flowing through the memory region.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: March 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chee-kheng Lim, Eun-sik Kim, Yong-su Kim
  • Patent number: 7901980
    Abstract: A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. Then defining a via in the insulating layers above the intermediate insulating layer, creating a channel for etch with a step spacer, defining a pore in the intermediate insulating layer, removing all insulating layers above the intermediate insulating layer, filling the entirety of the pore with phase change material, and forming an upper electrode above the phase change material. Additionally, the formation of bit line connections with the upper electrode.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Roger W. Cheek, Chung H. Lam, Stephen M. Rossnagel, Alejandro G. Schrott
  • Patent number: 7902643
    Abstract: Microfeature workpieces having interconnects and conductive backplanes and associated systems and methods are disclosed herein. One such device includes a semiconductor substrate having integrated circuitry and terminals electrically coupled to the integrated circuitry. The device also includes electrically conductive interconnects extending through at least a portion of the semiconductor substrate and electrically coupled to corresponding terminals. The device further includes a conductive backplane assembly having a conductive layer at a back side of the semiconductor substrate. One or more of the interconnects are electrically coupled to the conductive layer at the back side of the semiconductor substrate.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: March 8, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Patent number: 7902563
    Abstract: A long life light-emitting diode (LED) module is provided. The LED module includes: a light-emitting chip; a phosphor layer formed of phosphor materials that transform light emitted from the light-emitting chip into light having a longer wavelength than the light emitted from the light-emitting chip; a capping layer that is formed on the light-emitting chip and protects the light-emitting chip; and a heat spreading plate that is disposed between the capping layer and the phosphor layer that dissipates heat generated in the light-emitting chip and the phosphor layer.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: March 8, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yu-sik Kim, Hyung-kun Kim
  • Patent number: 7902583
    Abstract: A capacitor pair structure for increasing the match thereof has two finger electrode structures interlacing with each other in parallel and a common electrode being between the two finger electrode structures to form a capacitor pair structure with an appropriate ratio. Also, the capacitor pair structure could further increase its entire capacitance through vias connecting the same capacitor pair structures on different metal layers.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: March 8, 2011
    Assignee: Via Technologies, Inc.
    Inventor: Chih-Min Liu
  • Patent number: 7902087
    Abstract: An organic electroluminescent display device and a method of preparing the same are provided. The organic electroluminescent display device may include a first electrode formed on a substrate. A second electrode may be formed so as to be insulated from the first electrode. One or more organic layers may be interposed between the first electrode and the second electrode and include at least an emission layer. A protective layer may be formed so as to cover the second electrode. The protective layer may have a surface roughness (rms) of about 5 ? to about 50 ?. The organic electroluminescent display device including a protective layer having a low surface roughness may benefit from superior lifespan characteristics.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: March 8, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Dong-Won Han, Jin-Woo Park, Jang-Hyuk Kwon
  • Patent number: 7897495
    Abstract: Methods for formation of epitaxial layers containing silicon are disclosed. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the formation of the epitaxial layer involves exposing a substrate in a process chamber to deposition gases including two or more silicon source such as silane and a higher order silane. Embodiments include flowing dopant source such as a phosphorus dopant, during formation of the epitaxial layer, and continuing the deposition with the silicon source gas without the phosphorus dopant.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: March 1, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Zhiyuan Ye, Andrew M. Lam, Yihwan Kim
  • Patent number: 7897969
    Abstract: A solid-state image pickup device includes a pixel array area in which pixels each including a photoelectric conversion element are two-dimensionally arranged; first control means for performing control such that signals of pixels in a desired region of the pixel array area are sequentially read row by row; and second control means for performing control such that, when the signals of the pixels in the desired region are sequentially read row by row by the first control means, pixels in particular regions below and above the desired region are sequentially reset row by row.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: March 1, 2011
    Assignee: Sony Corporation
    Inventors: Yoshinori Muramatsu, Takahiro Abiru, Takaichi Hirata
  • Patent number: 7892962
    Abstract: A wafer-level chip-scale packaging feature for a semiconductor device is disclosed which has a substrate, a plurality of nail-shaped conducting posts extending from a surface of the substrate, and a plurality of solder balls, where each of the solder balls is connected to one of the nail-shaped conducting posts. When a different-sized solder ball is desired for use, the device can be re-processed by only removing and replacing the cross-members of the nail-shaped conducting posts, which cuts down on the re-processing expense.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: February 22, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chao-Yuan Su
  • Patent number: 7893458
    Abstract: A semiconductor device includes: a semiconductor substrate; a lateral MOS transistor disposed in the substrate; a Zener diode disposed in the substrate; and a capacitor disposed in the substrate. The transistor includes a drain and a gate, and the diode and the capacitor are coupled in series between the drain and the gate. This device has minimized dimensions and high switching speed. Further, both of a switching loss and a surge voltage are improved.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: February 22, 2011
    Assignee: DENSO CORPORATION
    Inventors: Shigeki Takahashi, Takashi Nakano, Nozomu Akagi, Yasushi Higuchi, Tetsuo Fujii, Yoshiyuki Hattori, Makoto Kuwahara, Kyoko Okada
  • Patent number: 7893512
    Abstract: An optoelectronic device that includes a material having enhanced electronic transitions. The electronic transitions are enhanced by mixing electronic states at an interface. The interface may be formed by a nano-well, a nano-dot, or a nano-wire.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: February 22, 2011
    Assignee: Los Alamos National Security, LLC
    Inventor: Marcie R. Black
  • Patent number: 7893510
    Abstract: A high temperature-stable sensor is provided in which electrodes on a substrate or an insulation layer are in contact with a sensitive layer, wherein the electrodes have platinum, rhodium, or iridium or an electrically conductive oxide layer. For this purpose, an intermediate product is provided as a platform chip, which has a deposited layer made of platinum, rhodium, or iridium or an alloy of platinum, rhodium, or iridium and is covered by an electrically conductive oxide. From the deposited layer, a conductive structure is formed and thus a platform chip is created with an electrically conductive structure subject to external influences. This structure has an electrically conductive oxide and/or its parts have long-term, stable characteristic resistance curves under high-temperature loading above about 500° C., especially between about 600° C. and 950° C. A sensor with a gas-sensitive layer formed as a gas-sensitive sensor is preferred.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: February 22, 2011
    Assignee: Heraeus Sensor Technology GmbH
    Inventors: Karlheinz Wienand, Karlheinz Ullrich
  • Patent number: 7888765
    Abstract: An optical semiconductor device includes a phototransistor for receiving incident light. The phototransistor includes a collector layer of a first conductivity type formed on a semiconductor substrate, a base layer of a second conductivity type formed on the collector layer, and an emitter layer of a first conductivity type formed on the base layer. A thickness of the emitter layer is equal to or less than an absorption length of the incident light in the semiconductor substrate.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: February 15, 2011
    Assignee: Panasonic Corporation
    Inventors: Masaki Taniguchi, Hisatada Yasukawa, Takaki Iwai
  • Patent number: 7888776
    Abstract: One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe seal integrity comprises a scribe seal structure that extends along at least a portion of the periphery of the integrated chip die and a detector test structure. The detector test structure and the scribe seal form an electrical system configured to be accessed for a monitoring of one or more electrical parameters to determine and characterize scribe seal integrity of the integrated circuit chip die. The results of the electric measurements are analyzed for statistically relevant reliability characterization. Other methods and circuits are also disclosed.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: February 15, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Ennis T. Ogawa, Honglin Guo, Joe W. McPherson
  • Patent number: 7888199
    Abstract: A semiconductor light-emitting transistor device, including: a bipolar pnp transistor structure having a p-type collector, an n-type base, and a p-type emitter; a first tunnel junction coupled with the collector, and a second tunnel junction coupled with the emitter; and a collector contact coupled with the first tunnel junction, an emitter contact coupled with the second tunnel junction, and a base contact coupled with the base; whereby, signals applied with respect to the collector, base, and emitter contacts causes light emission from the base by radiative recombination in the base.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: February 15, 2011
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Gabriel Walter, Nick Holonyak, Jr., Milton Feng, Richard Chan
  • Patent number: 7884465
    Abstract: A semiconductor package includes a semiconductor chip having bonding pads formed on a top surface and a first via hole and a second via hole formed on both-side edges; a passive element formed within the first via hole; a via wiring formed within the second via hole; a first wiring connected to the bonding pad at one end and connected to the passive element and the via wiring on a top surface of the semiconductor chip; a second wiring formed on a back surface of the semiconductor chip and formed to connect with the passive element and the via wiring; a first passivation film formed in such a way to expose one portion of the first wiring on a top surface of the semiconductor chip; and a second passivation film formed in such a way to expose one portion of the second wiring on a bottom surface of the semiconductor chip.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: February 8, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Taek Yang
  • Patent number: 7884376
    Abstract: An embodiment of the invention discloses an optoelectronic semiconductor device comprising a semiconductor system capable of performing a conversion between light energy and electrical energy; an interfacial layer formed on at least two surfaces of the semiconductor system; an electrical conductor; and an electrical connector electrically connecting the semiconductor system to the electric conductor.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: February 8, 2011
    Assignee: Epistar Corporation
    Inventors: Chih-Chiang Lu, Wei-Chih Peng, Shiau-Huei San, Min-Hsun Hsieh
  • Patent number: 7883955
    Abstract: A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr1) that is formed simultaneously in a first thermal oxidation process together with the formation of LOCOS isolation structures (3) for element seaaration of low voltage PMOS and NMOS transistors (Tr3, Tr4), and has a thinner gate dielectric layer (gate-insulation film 25 of, e.g., 7 nm) for a high voltage NMOS transistor (Tr2) that is formed simultaneously in a second thermal oxidation process together with the formation of gate dielectric layers (gate-insulation films 33, 42) of low voltage PMOS and NMOS transistors (Tr3, Tr4).
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: February 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Yoichi Okumura