Patents Examined by Wai-Sing Louie
  • Patent number: 8222667
    Abstract: Provided are a semiconductor light-emitting element that is capable of efficiently outputting blue color or ultraviolet light, and a lamp using the semiconductor light-emitting element. The semiconductor light-emitting element is obtained by a manufacturing method that, when manufacturing the semiconductor light-emitting element that comprises a compound semiconductor layer that includes at least a p-type semiconductor layer, and a transparent electrode that is provided on the p-type semiconductor layer, includes a step of forming a film comprising an oxide of indium and gallium, or forming a film comprising an oxide of indium, gallium and tin, in an amorphous state on the p-type semiconductor layer, so as to form a transparent conductive film, followed by a step of performing an annealing process on the transparent conductive film at a temperature of 200° C. to 480° C.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: July 17, 2012
    Assignee: Sumitomo Metal Mining Co., Ltd
    Inventors: Tokuyuki Nakayama, Yoshiyuki Abe
  • Patent number: 8218778
    Abstract: A method for showing an array microphone effect includes the steps of obtaining an original acoustic signal from array microphones, and visualizing the original acoustic signal to obtain a figure. The original acoustic signal includes a crystal voice, out-beam noises, background noise, and/or an echo. The figure includes a plurality of graphic components representing the crystal voice, out-beam noise, background noise, and/or echo, respectively.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: July 10, 2012
    Assignee: Fortemedia, Inc.
    Inventor: Bo-Ren Bai
  • Patent number: 8212300
    Abstract: After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: July 3, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kouichi Nagai
  • Patent number: 8212292
    Abstract: An improved bipolar transistor (40, 40?) is provided, manufacturable by a CMOS IC process without added steps. The improved transistor (40, 40?) comprises an emitter (48) having first (482) and second (484) portions of different depths (4821, 4841), a base (46) underlying the emitter (48) having a central portion (462) of a first base width (4623) underlying the first portion (482) of the emitter (48), a peripheral portion (464) having a second base width (4643) larger than the first base width (4623) partly underlying the second portion (484) of the emitter (48), and a transition zone (466) of a third base width (4644) and lateral extent (4661) lying laterally between the first (462) and second (464) portions of the base (46), and a collector (44) underlying the base (46). The gain of the transistor (40, 40?) is much larger than a conventional bipolar transistor (20) made using the same CMOS process.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: July 3, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xin Lin, Daniel J. Blomberg, Jiang-Kia Zuo
  • Patent number: 8212186
    Abstract: A plug-in heater for hot curlers is constituted in the following manner: because the power plug can be positioned at the storage location, it is constituted to possess a compact size; in particular, because the power plug can be positioned at the protruding positions in two perpendicular directions (a rear-side protruding direction and a lower-side protruding direction), the range for inserting the power plug can be expanded even when the electrical outlet is located at different locations at the housing facilities.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: July 3, 2012
    Assignee: Create Co., Ltd.
    Inventor: Kazutoshi Kaizuka
  • Patent number: 8208657
    Abstract: A signal processing device includes a sound pickup unit configured to pick up sound and convert the sound into a sound signal; a signal recording unit including an actuator that is driven by a current supplied from a power source and that has a possibility of generating audible noise caused by the driving, the signal recording unit being configured to record the sound signal therein; a current detecting unit configured to detect the magnitude of the current and a temporal change in the current; and a signal processing unit configured to determine, on the basis of at least one of the magnitude of the current and the temporal change in the current, whether the audible noise has been generated and perform, when it is determined that the audible noise has been generated, noise removal processing for removing the audible noise from the sound signal, which contains the audible noise.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: June 26, 2012
    Assignee: Sony Corporation
    Inventor: Hiroyuki Sano
  • Patent number: 8207549
    Abstract: An exemplary light emitting diode package includes a housing, and a light emitting unit received in the housing. The light emitting unit includes a first carbon nanotube layer, a plurality of spaced light emitting chips, and a second carbon nanotube layer. The light emitting chips are formed on the first carbon nanotube layer. The second carbon nanotube layer covers the light emitting chips.
    Type: Grant
    Filed: March 21, 2010
    Date of Patent: June 26, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Sei-Ping Louh
  • Patent number: 8207565
    Abstract: A semiconductor device includes: a stacked body including a conductive layer and an insulating layer alternately stacked on a base body; a pair of wall portions formed on the base body with a height equivalent to or larger than a thickness of the stacked body and opposed with a spacing wider than a thickness for one layer of the conductive layer; a contact layer interposed between the wall portions and connected to the conductive layer in the stacked body through an open end between the wall portions; and a contact electrode provided on the contact layer and connected to the contact layer.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: June 26, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koichi Sato
  • Patent number: 8203162
    Abstract: A light emitting device having a vertical structure and a method for manufacturing the same, which are capable of damping impact generated during a substrate separation process and achieving an improvement in mass productivity, are disclosed. The light emitting device includes a semiconductor layer having a multilayer structure, a first electrode arranged at one surface of the semiconductor layer, a metal support arranged on the first electrode, and an impact damping layer arranged between the first electrode and the metal support, and made of a metal having a ductility higher than a ductility of a metal for the metal support.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: June 19, 2012
    Assignees: LG Electronics Inc., LG Innotek Co., Ltd.
    Inventors: Jun Ho Jang, Hyun Jae Lee
  • Patent number: 8203141
    Abstract: Embodiments of the present invention are directed to a heterocyclic compound and an organic light-emitting device including the heterocyclic compound. The organic light-emitting devices using the heterocyclic compounds have high-efficiency, low driving voltages, high luminance and long lifespans.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: June 19, 2012
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Young-Kook Kim, Seok-Hwan Hwang, Yoon-Hyun Kwak, Hye-Jin Jung, Jong-Hyuk Lee, Hee-Joo Ko, Jin-O Lim
  • Patent number: 8204248
    Abstract: A system locates a speaker in a room containing a loudspeaker and a microphone array. The loudspeaker transmits a sound that is partly reflected by a speaker. The microphone array detects the reflected sound and converts the sound into a microphone signal. A processor determines the speaker's direction relative to the microphone array, the speaker's distance from the microphone array, or both, based on the characteristics of the microphone signals.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: June 19, 2012
    Assignee: Nuance Communications, Inc.
    Inventors: Tim Haulick, Gerhard Uwe Schmidt, Markus Buck, Tobias Wolff
  • Patent number: 8203159
    Abstract: A method of fabricating an optoelectronic device, comprising growing an active layer of the device on an oblique surface of a suitable material, wherein the oblique surface comprises a facetted surface. The present invention also discloses a method of fabricating the facetted surfaces. One fabrication process comprises growing an epitaxial layer on a suitable material, etching the epitaxial layer through a mask to form the facets having a specific crystal orientation, and depositing one or more active layers on the facets. Another method comprises growing a layer of material using a lateral overgrowth technique to produce a facetted surface, and depositing one or more active layers on the facetted surfaces. The facetted surfaces are typically semipolar planes.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: June 19, 2012
    Assignee: The Regents of the University of California
    Inventors: Hong Zhong, John F. Kaeding, Rajat Sharma, James S. Speck, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 8203174
    Abstract: An image sensor and a method for fabricating the same are provided. The image sensor includes a first conductive type substrate including a trench formed in a predetermined portion of the first conductive type substrate, a second conductive type impurity region for use in a photodiode, formed below a bottom surface of the trench in the first conductive type substrate, and a first conductive type epitaxial layer for use in the photodiode, buried in the trench.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: June 19, 2012
    Assignee: Intellectual Ventures II LLC
    Inventors: Hee Jeen Kim, Han Seob Cha
  • Patent number: 8202751
    Abstract: Provided are a flip-chip nitride-based light emitting device having an n-type clad layer, an active layer and a p-type clad layer sequentially stacked thereon, comprising a reflective layer formed on the p-type clad layer and at least one transparent conductive thin film layer made up of transparent conductive materials capable of inhibiting diffusion of materials constituting the reflective layer, interposed between the p-type clad layer and reflective layer; and a process for preparing the same. In accordance with the flip-chip nitride-based light emitting device of the present invention and a process for preparing the same, there are provided advantages such as improved ohmic contact properties with the p-type clad layer, leading to increased wire bonding efficiency and yield upon packaging the light emitting device, capability to improve luminous efficiency and life span of the device due to low specific contact resistance and excellent current-voltage properties.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: June 19, 2012
    Assignee: Samsung LED Co., Ltd.
    Inventors: Tae-Yeon Seong, June-O Song, Kyoung-Kook Kim, Woong-Ki Hong
  • Patent number: 8198648
    Abstract: An LED chip (1) grown on an electrically insulating substrate (4) comprises a lower current-distributing layer (5) of a first conductivity type, a first electrode (2), a vertical layer structure (5, 6, 7), the last two being formed on the lower current-distributing layer horizontally separated from each other, the vertical layer structure comprising an active layer (6) and an upper current-distributing layer (8) of a second conductivity type above the active layer, and a second electrode (3) formed on the upper current-distributing layer, the geometry of the electrodes being adjusted to provide a horizontal distance between the electrodes lower than the current spreading length of the chip. According to the present invention, a vertical trench (9) is formed between the electrodes (2, 3), the trench extending through the chip (1), including the lower current-distributing layer (5), for controlling the horizontal current flow in order to achieve a uniform current density over the active layer (6).
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: June 12, 2012
    Assignee: Optogan Oy
    Inventors: Vladislav E. Bougrov, Maxim A. Odnoblvudov
  • Patent number: 8199930
    Abstract: A pop noise suppression apparatus for eliminating popping noise generated upon initiation or shutdown of an audio output circuit comprises a switch component and a control circuit. The switch component allows the audio output circuit to provide audio through the output of the audio output circuit. The control circuit provides a mute signal for a first period of time in to response initiation or shutdown of the audio circuit. The control circuit comprises a capacitor to be charged upon initiation of the audio output circuit or to be discharged upon shutdown of the audio output circuit. A length of the first period of time during which the mute signal is provided depends on a second period of time to charge or discharge the capacitor.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: June 12, 2012
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Shih-Chien Wu
  • Patent number: 8198710
    Abstract: A multiple die package includes a folded leadframe for interconnecting at least two die attached to another leadframe. In a synchronous voltage regulator the folded leadframe, which is formed from a single piece of material, connects the high side switching device with the low side switching device to provide a low resistance, low inductance connection between the two devices.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: June 12, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Yong Liu, Tiburcio A. Maldo, Hua Yang
  • Patent number: 8198147
    Abstract: In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: June 12, 2012
    Assignee: GlobalFoundries, Inc.
    Inventors: Frank Feustel, Kai Frohberg, Thomas Werner
  • Patent number: 8199985
    Abstract: Methods for fully automatic quantification and interpretation of three dimensional images of the brain or other organs. A system for Computer Aided Diagnosis (CAD) of diseases affecting cerebral cortex from SPECT images of the brain, where said images may represent cerebral blood flow (CBF). The methods include image processing, statistical shape models, a virtual brain atlas, reference databases and machine learning.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: June 12, 2012
    Assignee: Exini Diagnostics Aktiebolag
    Inventors: David Jakobsson, Jens Richter, Andreas Järund
  • Patent number: 8193610
    Abstract: A semiconductor wafer contains a plurality of semiconductor die with bumps formed over contact pads on an active surface of the semiconductor die. A b-stage conductive polymer is deposited over the contact pads on the semiconductor wafer. The semiconductor wafer is singulated to separate the die. An insulating layer is formed over a carrier with openings formed in the insulating layer. The die is mounted to the carrier with the conductive polymer disposed in the openings of the insulating layer. The conductive polymer is heated to a glass transition temperature to liquefy the conductive polymer to an electrically conductive state. An encapsulant is deposited over the die and insulating layer. The carrier is removed to expose the conductive polymer. An interconnect structure is formed over the die, encapsulant, and conductive polymer. The interconnect structure is electrically connected through the conductive polymer to the contact pads on the die.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: June 5, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Reza A. Pagaila