Abstract: A portable data terminal includes at least two communication transceivers having different operating characteristics, one for conducting data communications on a wired subnetwork and one for conducting data communications on a wireless subnetwork. A communication processor converts data received by the communication transceivers to a predetermined format for a base module and converts data in a predetermined format from the base module to a format for transmission by a selected one of the first and second communication transceivers, thereby isolating the base module from differing characteristics of the transceivers. The communication processor is arranged to relay communications received by one transceiver for re-transmission by the other transceiver and to transfer communications from one subnetwork to the other, without activating the base module.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A data processor comprises an instruction decoding unit having two decoders decoding respective instructions of an instruction group consisting of a plurality of instructions including a first instruction and a second instruction succeeding the first instruction, and a judging unit judging whether or not a combination of the first instruction and the second instruction can be executed in parallel and a bus for transferring two data in parallel between an operand access unit and an integer operation unit. The data processor uses a superscalar technique. Two instructions having an operand interference can be executed in parallel at high speed and two instructions accessing a memory can be executed in parallel without considerable hardware.

Abstract: Coin-shaped one-wire communication modules with a flange for mounting convenience may be attached to contact extensions on items such as work totes for ease of communication. A host computer can keep track and locate multiple items which have mounted communication modules with use of a single data line and a single ground line for all of the modules.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A data transfer system includes a memory having first and second memory areas for storing information and being identified by different addresses, first and second address memories for storing the address of the first and second memory areas, and a central processing unit for reading information from the first memory area on the basis of the address stored in the first address memory. The central processing unit also writes new information in the first memory area on the basis of the address stored in the first address memory, and also stores the information read from the first memory area in the second memory area on the basis of the address stored in the second address memory. In addition, the second memory area can have a portion called a common area, in common with the first memory area. The central processing unit can read information from the first memory area including this common area on the basis of the address in the first address memory.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A data processing apparatus (71) includes a data processor bus (103), the rotation register (208) and a register selection circuit. The rotation register (208) is embodied by a plurality of data registers (200) each having a plurality of equal bit groups. The number of bits within each bit group of each data register preferably equals the number N of data registers. The register selection circuit permits normal register reads and writes via the data processor bus. The register selection circuit permits special rotational data accesses. In a rotation read mode the register selection circuit selects noncontiguous bits from a predetermined position within each sections for each of the data registers for read access. In a rotation write mode the register selection circuit selects noncontiguous bits from a predetermined position within each sections for each of the data registers for write access. The data registers (200) are connected together in a loop (208).

Abstract: Creators of computer software provide the most up-to-date versions of their computer software on an update service. A user who has purchased or downloaded free computer software calls an update service or a network service provider (e.g., an Internet provider) on a periodic basis. The update or network service automatically inventories the user computer to determine what computer software (e.g., a network browser) may be out-of-date, and/or need maintenance updates. If so desired by the user, the update service computer automatically downloads with a secure software transfer process and installs computer software to the user computer. By making periodic calls to an update or network service, the user always has the most up-to-date computer software immediately available. The update or network service may also alert the user to new products (i.e. including new help files, etc.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: This invention is a technique for summing plural sections of a single data word. The technique uses a repeated process forming larger and larger partial sums. Initially the single data word is rotated one section. The original single data word and the rotated single data word are masked with a mask having "1's" and "0's" in alternate sections. The mask blocks alternate sections so that adjacent sections of the original data word may be summed on a whole data word basis without any overflow disrupting the partial products. The two masked data words are then summed. This sum results in half as many partial sums as before. Each of these larger partial sums now occupies two original sections of the data word. The process can be repeated for these large partial sums. In the preferred embodiment this technique is used with an arithmetic logic unit (230) capable of forming mixed arithmetic and Boolean combinations of three inputs having a barrel rotator (235) driving one input.

Abstract: Coin-shaped one-wire communication modules with a flange for mounting convenience may be attached to contact extensions on items such as work totes for ease of communication. A host computer can keep track and locate multiple items which have mounted communication modules with use of a single data line and a single ground line for all of the modules.

Abstract: A method is provided for writing a scalar value to a vector V1 without reading the vector from a storage device. A scalar value to be written into the vector at a specified position and a scalar value (index) representing such position are read from a storage device into an Arithmetic Logic Unit (ALU) of a vector processor. The ALU then generates another vector V2 having multiple copies of the scalar value to be written into V1. ALU also generates a mask representing the index. The vector V2 is then delivered to the storage storing V1, but the mask is applied so that only one or more, but not all, copies of the scalar value are written from V2 to the storage. The rest of the vector V1 remains unchanged. The invention reduces register file read contention. Furthermore, if the updated V1 (i.e. V1 having the scalar value) is to be used in the next instruction, a copy of V1 is read from the storage and is updated from V2 and the mask, simultaneously with V1 being updated in the storage.

Abstract: A method and an apparatus for confirming matching of data in a distributed processing system aiming easy maintenance of the matching of the data and efficient parallel design work in a distributed processing system. In the distributed processing system having a server including a database and plural clients utilizing data in the database, said server and clients are connected to each other. The server stores information of destinations to which data in the database has been distributed and receives information of an editorial history of the data from a client that is a destination of the distributed data to store the editorial history information at the destination client on the side of the server. After that, matching of the data is confirmed on the side of another client on the basis of the distributed data's destination information or the editorial history information stored in the server.

Abstract: A network or interconnect structure utilizes a data flow technique that is based on timing and positioning of messages communicating through the interconnect structure. Switching control is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided. The interconnect structure operates as a "deflection" or "hot potato" system in which processing and storage overhead at each node is minimized. Elimination of a global controller and buffering at the nodes greatly reduces the amount of control and logic structures in the interconnect structure, simplifying overall control components and network interconnect components and improving speed performance of message communication.

Abstract: In a data processing apparatus, a decoding unit decodes instructions. A calculator operates N-bit data in accordance with the decoded results. A flag storage unit stores a plurality of flag groups which are changed in correspondence to data having different widths, based on the operated results. Selectors select a predetermined flag group in accordance with the direction of a conditional branch instruction. A branch judging unit judges whether a branch is taken or not by referring to the selected flag group.

Abstract: A computer apparatus for receiving a removable communication card such as a radio card or a modem card. A radio or modem is self-contained inside a housing of the communication card and has an electrical interface for communicating information to and from the computer apparatus. The computer apparatus receives the communication card such that it engages the electrical interface. The computer apparatus additionally has at least one pair of electrical contacts which will encounter electrical contacts on the communication card. These contacts automatically connect the communication card to an appropriate antenna, telephone, telephone line or power source. A radio communication card is connected to the appropriate antenna for the type and frequency of the radio. A modem card is connected to a standard telephone line, a cellular phone, or an antenna for a cellular phone if the cellular phone is also disposed within the housing of the modem communication card.

Abstract: A system and method for generating a program to enable reassignment of data items among processors in a massively-parallel computer to effect a predetermined rearrangement of address bits. The computer has a plurality of processing elements, each including a memory. Each memory includes a plurality of storage locations for storing a data item, each storage location within the computer being identified by an address, comprising a plurality of address bits having a global portion comprising a processing element identification portion and a local portion identifying the storage location within the memory of the particular processing element. The system generates a program to facilitate use of a predetermined set of tools to effect a reassignment of data items among processing elements and storage location to, in turn, effect a predetermined rearrangement of address bits. The system includes a global processing portion and a local processing portion.

Abstract: A processor node which includes at least one local bus (10) that assures a parallel link among the processors (8), a local memory (11) and a shared cache (12), and one network bus (13) that assures a parallel link among the local memory (11), the shared cache (12), and at least one input/output device (6).