Patents Examined by Walter D. Davis
  • Patent number: 5781738
    Abstract: A process for terminating a client server network connection that includes a first automatic termination of all programs executing on the client from code accessed from the server. The disconnection processing interrogates the client computer system to determine any open program files or libraries. Network program files or libraries result in a user prompting to determine whether they should be automatically terminated. In an alternate embodiment, a profile may indicate whether automatic termination will take place without user notification. Once all network loaded programs have been terminated, the disconnection process proceeds normally to sever the network connection.
    Type: Grant
    Filed: July 24, 1996
    Date of Patent: July 14, 1998
    Assignee: International Business Machines Corporation
    Inventors: Vance Edward Corn, Steven Michael French
  • Patent number: 5781725
    Abstract: In a computer network system having client and server computers (26,27), an access right check requesting section (28) of the client computer supplies a user certification datum to a access right checking section (32) of the server computer. The access right checking section (32) checks a name of a user and a password of the user certification datum with predetermined held names of users and predetermined held passwords to produce and supply a certification result datum to a client certification result holding section (29) of the client computer when the name of the user coincides with the one of predetermined held names of the users and when the password coincides with the one of predetermined held passwords. A process requesting section (30) compares the certification result datum of the client certification result holding section (29) with the user certification datum which is supplied with a process requesting command having the user certification datum.
    Type: Grant
    Filed: May 23, 1996
    Date of Patent: July 14, 1998
    Assignee: NEC Corporation
    Inventor: Katsumi Saito
  • Patent number: 5778429
    Abstract: A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.
    Type: Grant
    Filed: July 3, 1995
    Date of Patent: July 7, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Naonobu Sukegawa, Tshiaki Tarui, Hiroaki Fujii, Hideya Akashi
  • Patent number: 5774698
    Abstract: A generic network device includes a serial line switching apparatus for performing either parallel or serial communications amongst multiple nodes over switching networks. An aspect includes is the adaptation of standard and proprietary serial interfaces using either optical or electrical transmission media to interface to the parallel switch. The converted serial data is routed to the selected destination through the parallel switch network, where it is received and converted back into a serial optical or electrical interface/protocol. Thus, the combination of the switching adapter and an ALLNODE parallel switching network make it feasible for serial message data to be switched and routed to various destinations.
    Type: Grant
    Filed: March 3, 1997
    Date of Patent: June 30, 1998
    Assignee: International Business Machines Corporation
    Inventor: Howard Thomas Olnowich
  • Patent number: 5764920
    Abstract: A system and method for routing administrative data over a telecommunications network to a remote processor establishes a connection between a router and the remote processor over a primary link. A processor associated with the router is adapted to detect a predetermined condition and thereupon to automatically reconfigure the router to establish another connection with the remote processor or a connection with another remote processor. The data may be routed over a telecommunications switching network using a router having inverse multiplexing capability. Further, a sockets connection may be established between the associated processor and the remote processor for monitoring the status of the connection between the router and the remote processor to detect a predetermined condition such as a link failure. External customer data may be routed to the system for remote archival purposes.
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: June 9, 1998
    Assignee: Sprint Communications Co. L.P.
    Inventors: Fred Samuel Cook, Michael Dean Edwards, Scott Bruce Wilson
  • Patent number: 5761200
    Abstract: The present invention discloses a distributed data transfer system for transferring data among several processing units and an integrated data storage means, e.g., a memory sub-system. The distributed data transfer system includes a plurality of distributed data transfer means for connecting to the processing units. The distributed data transfer system further includes a distribution control means connected to the distributed data transfer means and the integrated data storage means. The distributed data transfer means, under the control of the distribution control means, is capable of transferring the data in divisible portions over a plurality of scheduled time periods. In a preferred embodiment, the distributed data transfer means further includes a plurality of data bus branches and a bus trunk connecting to the data bus branches. The distribution control means further includes a programmable control means for down-loading of control programs for controlling the distributed data transfers.
    Type: Grant
    Filed: October 27, 1993
    Date of Patent: June 2, 1998
    Assignee: Industrial Technology Research Institute
    Inventor: Hsun-Chang Hsieh
  • Patent number: 5761522
    Abstract: The present invention provides a program control system including plural programs, plural execution means each of which executes the corresponding program of the plural programs, a memory for storing the plural programs, plural program counters each of which generates an address for reading the corresponding one of the programs from the memory, and a selector for selecting an output of one of the program counters and providing the output to the memory. Each of the programs stored in the memory and executed by the corresponding one of the execution means is indicated by the address generated by the corresponding one of the program counters selected by the selector, and the memory sequentially stores instructions in each of the programs.
    Type: Grant
    Filed: April 18, 1996
    Date of Patent: June 2, 1998
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Takanori Hisanaga, Fumiyoshi Kawase, Koh Kamizawa
  • Patent number: 5761415
    Abstract: A naming service maintains lists of names for receiving messages, with the names having a defined format portion for routing messages in the network. At least some names have additional routing information that is passed to another server or service for routing the messages externally, such as with remote e-mail or facsimile transmission.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: June 2, 1998
    Assignee: Banyan Systems, Inc.
    Inventors: Brett Joseph, Kathleen McConnell
  • Patent number: 5757685
    Abstract: An arithmetic and logic operation system capable of performing an arithmetic and logic operation for data longer than one word, includes an arithmetic and logic unit for performing an arithmetic and logic operation for a less significant one-word length portion of the data, and an incrementer/decrementer for incrementing or decrementing of a more significant data portion exceeding the one-word length of the data. A carry signal or a borrow signal generated in the arithmetic and logic unit is supplied to the incrementer/decrementer so that the incrementer/decrementer is controlled so as to selectively increment, or decrement the received data or alternately to output the received data without modification.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: May 26, 1998
    Assignee: NEC Corporation
    Inventor: Mitsurou Ohuchi
  • Patent number: 5754764
    Abstract: Input/output and local area network functions are combined into a single integrated circuit on a single semiconductor (e.g., a single piece of silicon). Preferred system embodiments on a single integrated circuit are typically placed inside a host system (e.g., a personal computer based on Intel.RTM.'s 286, 386, 486, and Pentium microprocessors) and interrelate with standard operating systems (e.g., Microsoft.RTM.'s DOS, IBM.RTM.'s OS/2) on traditional, commonly used bus architectures (e.g., Industry Standard Architecture and Enhanced Industry Standard). Local area network circuitry and input and output circuitry are both coupled to at least one host system (and indirectly to potentially any number of host systems tied together via the local area network system) via a common data bus. The input and output circuitry couples the host system to at least one input/output channels.
    Type: Grant
    Filed: February 22, 1994
    Date of Patent: May 19, 1998
    Assignee: National Semiconductor Corp.
    Inventors: Timothy D. Davis, Roman Baker, Dan E. Daugherty, Martin S. Michael, Ahmed Masood, Kent Bruce Waterson, Hon C. Fung, Mark Douglas Koether, J. Scott Johnson
  • Patent number: 5752073
    Abstract: A digital signal processing architecture is inherently cyclical in nature, by providing a timer which can be programmed to reset the processor and return to the first instruction periodically, typically once each sample of the input sample stream. Pipeline operation is enhanced through the use of a double buffering system in which operands are latched into the first stage of a double buffer as soon as they are ready, but they are transferred to the second stage only when the last-ready operand is available and the computation unit is ready to receive the operands. The computation unit receives the operands in the second stage of the buffers. The processor communicates with an external unit via a random access memory and a plurality of FIFOs. Each FIFO is associated with a respective location in the random access memory. Whenever the processor retrieves a value from one of these locations in the random access memory, control means automatically refills that location from the corresponding FIFO.
    Type: Grant
    Filed: July 11, 1995
    Date of Patent: May 12, 1998
    Assignee: CagEnt Technologies, Inc.
    Inventors: Donald M. Gray, III, David L. Needle
  • Patent number: 5748917
    Abstract: A data system architecture and interface circuits permit slow devices having limited signal capacities to launch and receive information from a central bus. Data is clocked onto the bus with a master circuit at the leading and trailing edges of the bus clock so that portions of a large multibit signal are launched without having to wait for the initiation of a next clock cycle. Accordingly, data portions are launched during both leading and trailing edges of the clock signal. In the case of a simple bus device not able to accommodate inclusion of a slave interface circuit, the received signal packet is provided in adapted form anticipating that only a second half portion of the signal packet will actually be registered as received.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: May 5, 1998
    Assignee: Apple Computer, Inc.
    Inventors: William Todd Krein, Charles M. Flaig, James D. Kelly
  • Patent number: 5745779
    Abstract: A network system for a parallel processor system includes network subsystems connecting processor units to each other, where contention generated in communication between the processor units is restrained so as to increase the throughput of the system, improve the extensibility of the system, and enable the system to be formed by an amount of materials depending on a scale of the system.
    Type: Grant
    Filed: September 28, 1994
    Date of Patent: April 28, 1998
    Assignee: Fujitsu Limited
    Inventor: Masayuki Katori
  • Patent number: 5742785
    Abstract: Using this invention, more than one variable that is shared in a multiprocessing environment can be updated atomically. Each computer processor operating in the multiprocessing environment contains more than one reservation register which, along with this novel method, are used to place reservations on each of more than one shared variable. During the execution of a program, a plurality of shared variables can be reserved, each by its respective reservation register. A reservation is placed on a shared variable by means of a special instruction. The reservation register keeps track of: the address of the shared variable that it is reserving, the value of the modified results that are to be updated in the shared variable address, whether the variable has been updated, whether the reservation is valid, and whether the processor containing the reservation register has a privilege to update the shared variable.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: April 21, 1998
    Assignee: International Business Machines Corporation
    Inventors: Harold Stuart Stone, Janice Murphy Stone
  • Patent number: 5737319
    Abstract: A system and method for dynamically determining the physical connection topology between diverse network elements (DNEs) within a communication network. Each DNE is audited on a periodic basis to determine the arrangement, configuration, cross-connection, and alarm status of each communication port within each DNE in the communications network. A topology database is maintained with such baseline information. Each DNE is configured with at least one mismatched port. Mismatched ports are cross-connected with communication ports within DNEs so that signal mismatch alarms are generated by communication ports coupled with the mismatched ports in other DNEs. Signal mismatch alarms are collected and processed so that connectivity status may be derived based on the baseline data, expected alarms, and the receipt of such alarms or lack thereof. A topology database is continuously updated to reflect such derived information.
    Type: Grant
    Filed: April 15, 1996
    Date of Patent: April 7, 1998
    Assignee: MCI Corporation
    Inventors: William D. Croslin, Mark W. Sees, Perry Voyles
  • Patent number: 5737542
    Abstract: The size of the address space to be occupied by an expanded board installed into a slot is identified, and the corresponding relationship between an address of a computer and a slot selection signal for selecting any one of the slots is set in a mapping table on the basis of the identification result, whereby the address space to be occupied by the expanded board is adaptably allocated on an address space of the computer.
    Type: Grant
    Filed: October 10, 1995
    Date of Patent: April 7, 1998
    Assignee: Sony Corporation
    Inventors: Ken Kurihara, Hiroshi Tezuka, Hiroyuki Kobayashi
  • Patent number: 5737632
    Abstract: A disc storage apparatus includes a disc having at least one recording surface, a head associated with the recording surface for recording data on the recording surface during a data write operation, and for reproducing data from the recording surface during a data read operation, a disc control unit for receiving data and outputting parallel data during the data write operation, and for receiving parallel data and outputting data during the data read operation, and an encoder/decoder circuit for receiving the parallel data from the disc control unit and outputting data to the head to be recorded on the recording surface during the data write operation, and for receiving from the head data reproduced from the recording surface and outputting parallel data to the disc control unit during the data read operation.
    Type: Grant
    Filed: February 22, 1994
    Date of Patent: April 7, 1998
    Assignees: Hitachi, Ltd., Hitachi Video Engineering, Incorporated
    Inventors: Takashi Oeda, Motoyasu Tsunoda, Noriyuki Karasawa, Yukihito Takada, Satoshi Kawamura, Yoshio Yukawa, Tsuneo Hirose, Mitsuru Kubo
  • Patent number: 5734900
    Abstract: An information handling system includes one or more processing units, a data management unit, connected to the processor data bus, to a memory system, and to a I/O bus, an address management unit, connected to the processor address bus, to the memory system, to an I/O bus, and to a system initialization storage device, storing an initialization routine and data, wherein system initialization includes, in response to an Initial Program Load Read command issued by a processor, the steps of returning initialization data to the processor if the IPL read is accepted (IPL data available) by a device attached to the processor bus; if no device attached to the processor bus responds with IPL data, passing the read IPL command to the I/O bus under control of the data management unit; if the read command is accepted by an I/O controller attached to the I/O bus, returning initialization data to the processor; if no I/O controller accepts the IPL read command, passing the read command to the system initialization storage
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: March 31, 1998
    Assignee: International Business Machines Corporation
    Inventors: John Michael Kaiser, Warren Edward Maule
  • Patent number: 5734921
    Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32 K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: March 31, 1998
    Assignee: International Business Machines Corporation
    Inventors: Michael Charles Dapp, James Warren Dieffenderfer, Richard Ernest Miles, Richard Edward Nier, Vincent John Smoral, James Robert Stupp
  • Patent number: 5732233
    Abstract: A data processing apparatus has a number of data processors connected in a series by data lines so that data signals are processed in a preceding processor and communicated to a succeeding processor in the series. The apparatus has a number of control elements, where a control element has first and second inputs receiving processor status signals and an output sending a signal to enable processing. The control element output assumes a certain output state only if both inputs assume the state. The output, having assumed the state, holds the state, despite one of the inputs not holding the state, only if a certain one of the inputs does hold the state.
    Type: Grant
    Filed: January 23, 1995
    Date of Patent: March 24, 1998
    Assignee: International Business Machines Corporation
    Inventors: Peter Juergen Klim, Nandor G. Thoma