Patents Examined by Wasiul Haider
  • Patent number: 11031577
    Abstract: A multimodal light-emitting OLED microcavity device, comprising: an opaque substrate; a layer with a reflective surface over the substrate; a first electrode over the reflective surface; organic layers for light-emission including a second blue light-emitting layer closer to the reflective surface and a first blue light-emitting layer further from the reflective layer than the second blue light-emitting layer, where the distance between the midpoints of the second and first blue-light emitting layers is L1, and at least one non-blue light-emitting layer; a semi-transparent second electrode with an innermost surface through which light is emitted; wherein the distance L0 between the reflective surface and the innermost surface of the semi-transparent second electrode is constant over the entire light-emitting area; and the ratio L1/L0 is in the range of 0.30-0.40. The multimodal microcavity OLED has increased blue emission and is particularly useful for use as the light source in a microdisplay.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: June 8, 2021
    Assignee: OLEDWorks LLC
    Inventors: John Hamer, Donald Preuss, Shane Matesic
  • Patent number: 11018049
    Abstract: A manufacturing method of an isolation structure includes the following steps. A semiconductor substrate is provided. A trench is formed in the semiconductor substrate. A first film forming process is performed to form a first dielectric layer conformally on the semiconductor substrate and conformally in the trench. An annealing process is performed to densify the first dielectric layer and convert the first dielectric layer into a second dielectric layer. A thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A second film forming process is performed after the annealing process to form a third dielectric layer on the second dielectric layer and in the trench. The trench is filled with the second dielectric layer and the third dielectric layer.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: May 25, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Shan Su, Chia-Wei Wu
  • Patent number: 11004838
    Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen
  • Patent number: 11004761
    Abstract: The present invention provides a semiconductor device including an insulating layer, a conductive layer bonded to one main surface of the insulating layer, a semiconductor element arranged such that the upper surface of the semiconductor element faces a direction same as the one main surface of the insulating layer, an upper electrode provided on the upper surface of the semiconductor element, a wiring member that has one end electrically bonded to the upper electrode of the semiconductor element and has another end electrically bonded to the conductive layer, and has a hollow portion, a first sealing material, and a second sealing material, in which the first sealing material seals at least part of the semiconductor element so as to be in contact with the semiconductor element, and the second sealing material seals the wiring member so as to be in contact with the wiring member.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: May 11, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Soichi Sakamoto, Junji Fujino, Hiroshi Kawashima, Taketoshi Maeda
  • Patent number: 10998409
    Abstract: An integrated circuit includes a Laterally Diffused MOSFET (LD-MOSFET) located over a semiconductor substrate. The LD-MOSFET transistor includes a dielectric filled trench at a surface of the semiconductor substrate, and a doped region of the semiconductor substrate adjacent the dielectric-filled trench. The doped region and the dielectric-filled trench share an interface that has a terminus at the surface of the semiconductor substrate. An oxide layer is located over the semiconductor substrate, including along a surface of the doped region and along a surface of the dielectric-filled trench. The oxide layer has a first thickness over the dielectric-filled trench and a second greater thickness over the doped region.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 4, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jun Cai
  • Patent number: 10964661
    Abstract: The present invention comprises: a spool (10); a clamper (22); a torch electrode (31); a high-voltage power source circuit (30); a non-bonding detection circuit (40); a first changeover switch (50) switching a connection between the spool (10) and the high-voltage power source circuit (30) or the non-bonding detection circuit (40); and a relay (53) turning on/off a connection between the clamper (22) and a spool side of the first changeover switch (50), and comprises a control part (60) that sets the first changeover switch (50) to the high-voltage power source circuit side and turns off the relay (53) to generate electric discharge, and that sets the first changeover switch (50) to the non-bonding detection circuit side and turns on the relay (53) to perform non-bonding detection. Due to this configuration, electric corrosion of a wire clamper can be suppressed and non-bonding detection can be carried out with a simple configuration.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: March 30, 2021
    Assignee: SHINKAWA LTD.
    Inventors: Junichi Abe, Hisashi Ueda, Yutaka Kondo
  • Patent number: 10957823
    Abstract: A light emitting device according to an embodiment includes a body having a recess; a light emitting chip disposed in the recess; and a first dampproof layer sealing the light emitting chip and extended from a surface of the light emitting chip to a bottom of the recess, wherein the light emitting chip includes a wavelength range of 100 nm to 280 nm, and the first dampproof layer includes a fluororesin-based material.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 23, 2021
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jae Jin Kim, Do Hwan Kim
  • Patent number: 10950612
    Abstract: A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: March 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sunggil Kim, Sangsoo Lee, Seulye Kim, Hongsuk Kim, Jintae Noh, Ji-Hoon Choi, Jaeyoung Ahn, Sanghoon Lee
  • Patent number: 10943813
    Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: March 9, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Michael R. Seacrist, Robert W. Standley, Jeffrey L. Libbert, Hariprasad Sreedharamurthy, Leif Jensen
  • Patent number: 10943942
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a device layer and a trench isolation. The semiconductor substrate has a front side surface and a back side surface opposite to the front side surface. The radiation sensing member is disposed in a photosensitive region of the semiconductor substrate and extends from the front side surface of the semiconductor substrate. The radiation sensing member includes a semiconductor material with an optical band gap energy smaller than 1.77 eV. The device layer is over the front side surface of the semiconductor substrate and the radiation sensing member. The trench isolation is disposed in an isolation region of the semiconductor substrate and extends from the back side surface of the semiconductor substrate.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu Wei, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Patent number: 10937935
    Abstract: A light emitting diode chip includes: a first conductivity type semiconductor layer; a mesa disposed on a partial region of the first conductivity type semiconductor layer, and including an active layer and a second conductivity type semiconductor layer; a transparent electrode being in ohmic contact with the second conductivity type semiconductor layer; a first current spreader being in ohmic contact with the first conductivity type semiconductor layer; a second current spreader electrically connected to the transparent electrode; an insulation layer covering the mesa, the first current spreader and the second current spreader, and including a distributed Bragg reflector. A lateral distance between the first current spreader and the mesa is larger than a thickness of the insulation layer, and a first side surface of the first current spreader close to the mesa is longer than the second side surface thereof.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: March 2, 2021
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jin Woong Lee, Kyoung Wan Kim, Keum Ju Lee
  • Patent number: 10937751
    Abstract: Provided is a method of manufacturing a bump structure, the method including a first step for preparing a wafer including a plurality of chips each including a die pad, an under bump metal (UBM) layer on the die pad, and a bump pattern on the UBM layer, a second step for attaching a backgrinding film to an upper surface of the wafer, a third step for grinding a rear surface of the wafer by a certain thickness, a fourth step for forming a flexible material layer on a second rear surface of the wafer after being ground, and then attaching dicing tape including a ring frame, to the flexible material layer, a fifth step for removing the backgrinding film and then performing a curing process to harden the flexible material layer, and a sixth step for performing a dicing process to cut the plurality of chips into individual chips.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 2, 2021
    Assignee: LBSEMICON CO., LTD.
    Inventor: Jin Kuk Lee
  • Patent number: 10937906
    Abstract: A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first to a third stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun Hsiung Tsai, Kei-Wei Chen
  • Patent number: 10935515
    Abstract: Methods and devices for a stacked nanofluidic sensor are described. The stacked nanofluidic sensor and methods for forming a nanosheet stack of at least two alternating layers of a first nanosheet material and a second nanosheet material on a substrate. Additionally, a gate structure is formed on the nanosheet stack. Further, nanofluidic channels are formed within the gate structure, including removing each layer of the first nanosheet material within the gate structure to form a channel configured to receive a nanofluidic sample.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kangguo Cheng
  • Patent number: 10930567
    Abstract: A method is presented for forming a transistor having reduced parasitic contact resistance. The method includes forming a first device over a semiconductor structure, forming a second device adjacent the first device, forming an ILD over the first and second devices, and forming recesses within the ILD to expose the source/drain regions of the first device and the source/drain regions of the second device. The method further includes forming a first dielectric layer over the ILD and the top surfaces of the source/drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source/drain regions of the second device resulting in second dielectric layers formed over the source/drain regions of the second device, and forming an epitaxial layer over the source/drain regions of the first device after removing remaining portions of the first dielectric layer.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Shogo Mochizuki, Chun Wing Yeung, Hemanth Jagannathan
  • Patent number: 10916422
    Abstract: Disclosed is a wafer or a material stack for semiconductor-based optoelectronic or electronic devices that minimizes or reduces misfit dislocation, as well as a method of manufacturing such wafer of material stack. A material stack according to the disclosed technology includes a substrate; a basis buffer layer of a first material disposed above the substrate; and a plurality of composite buffer layers disposed above the basis buffer layer sequentially along a growth direction. The growth direction is from the substrate to a last composite buffer layer of the plurality of composite buffer layers. Each composite buffer layer except the last composite buffer layer includes a first buffer sublayer of the first material, and a second buffer sublayer of a second material disposed above the first buffer sublayer. The thicknesses of the first buffer sublayers of the composite buffer layers decrease along the growth direction.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: February 9, 2021
    Assignee: Xiamen Changelight Co., Ltd.
    Inventors: Kaixuan Chen, Wei Jiang, Zhiwei Lin, Xiangjing Zhuo, Tianzu Fang, Yang Wang, Jichu Tong
  • Patent number: 10910405
    Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Patrick Morrow, Stephen M. Cea, Rishabh Mehandru, Cory E. Weber
  • Patent number: 10903458
    Abstract: An optoelectronic assembly comprising an optoelectronic component, which comprises a specularly reflective surface and comprising a radiation cooler in direct physical contact with the optoelectronic component. The radiation cooler is arranged above the specularly reflective surface.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: January 26, 2021
    Assignee: PICTIVA DISPLAYS INTERNATIONAL LIMITED
    Inventors: Dominik Pentlehner, Richard Baisl
  • Patent number: 10896970
    Abstract: A process of forming a field effect transistor (FET) of a type of high electron mobility transistor (HEMT) reducing damages caused in a semiconductor layer is disclosed. The process carries out steps of: (a) depositing an insulating film on a semiconductor stack; (b) depositing a conductive film on the insulating film; (c) forming an opening in the conductive film and the insulating film by a dry-etching using ions of reactive gas to expose a surface of the semiconductor stack; and (d) forming a gate electrode to be in contact with the surface of the semiconductor stack through the opening, the gate electrode filling the opening in the conductive film and the insulating film.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: January 19, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventors: Tadashi Watanabe, Hajime Matsuda
  • Patent number: 10886214
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kanta Saino