Patents Examined by Wasiul Haider
  • Patent number: 10707450
    Abstract: Disclosed is an OLED thin film packaging structure, including: a TFT substrate, an OLED, a first barrier layer, a first buffer layer, and a second barrier layer. The OLED is disposed on the TFT substrate. The first barrier layer is disposed on four sides and an upper surface of the OLED. The first buffer layer is disposed on an upper surface of the first barrier layer, and the second barrier layer covers the first barrier layer and the first buffer layer. An OLED thin film packaging method includes steps of: preparing a first barrier layer and a first buffer layer by using a first mask, and preparing a second barrier layer by using a second mask, thereby reducing a quantity of times for changing a mask, reducing a quantity of particles, and improving a thin film packaging effect.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: July 7, 2020
    Inventor: Wei Yu
  • Patent number: 10707216
    Abstract: Provided is a method for manufacturing a semiconductor device including: patterning a substrate to form a plurality of active patterns including two adjacent active patterns having a first trench therebetween; forming a semiconductor layer on the plurality of active patterns to cover the plurality of active patterns; forming a device isolation layer on the semiconductor layer to cover the semiconductor layer for oxidization and fill the first trench; patterning the device isolation layer and the plurality of active patterns so that a second trench intersecting the first trench is formed and the two active patterns protrudes from the device isolation layer in the second trench; and forming a gate electrode in the second trench. Here, a first thickness of the semiconductor layer covering a top surface of each of the two active patterns is greater than a second thickness of the semiconductor layer covering a bottom of the first trench.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 7, 2020
    Inventors: Sungmi Yoon, Chunhyung Chung
  • Patent number: 10707379
    Abstract: An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include an n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary, which has a shape including a plurality of interconnected fingers. The n-type semiconductor layer can have a shape at least partially defined by the mesa boundary. A first n-type contact layer can be located adjacent to another portion of the n-type semiconductor contact layer, where the first n-type contact layer forms an ohmic contact with the n-type semiconductor layer. A second contact layer can be located over a second portion of the n-type semiconductor contact layer, where the second contact layer is formed of a reflective material.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: July 7, 2020
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Alexander Dobrinsky, Maxim S. Shatalov, Mikhail Gaevski, Michael Shur
  • Patent number: 10700212
    Abstract: A semiconductor device includes a first insulator, a transistor over the first insulator, a second insulator over the transistor, and a third insulator over the second insulator. The transistor includes an oxide semiconductor. The amount of oxygen released from the second insulator when converted into oxygen molecules is larger than or equal to 1×1014 molecules/cm2 and smaller than 1×1016 molecules/cm2 in thermal desorption spectroscopy at a surface temperature of a film of the second insulator of higher than or equal to 50° C. and lower than or equal to 500° C. The second insulator includes oxygen, nitrogen, and silicon.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: June 30, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromi Sawai, Akihisa Shimomura
  • Patent number: 10685934
    Abstract: A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: June 16, 2020
    Inventors: Jen-Kuang Fang, Wen-Long Lu
  • Patent number: 10686053
    Abstract: A high electron mobility transistor (HEMT) includes a semiconductor layer on a substrate; an insulating film on the semiconductor layer; a gate electrode in contact with a surface of the semiconductor layer through an opening in the insulating film; and a conductive film provided between the insulating film and a portion of the gate electrode at peripheries of the opening. The insulating film and the conductive film are made of respective materials containing silicon (Si). The gate electrode includes a Schottky metal in contact with the semiconductor layer and a cover metal provided on the Schottky metal. The Schottky metal covers the conductive film thereunder.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 16, 2020
    Inventors: Tadashi Watanabe, Hajime Matsuda
  • Patent number: 10672801
    Abstract: The present invention provides a TFT substrate. The TFT substrate includes: a first display area and a second display area that are sequentially arranged in a vertical direction. Main pixel electrodes and sub pixel electrodes of the first display area are arranged in mirror symmetry with respect to main pixel electrodes and sub pixel electrodes of the second display area, respectively, about a horizontal division line of the first display area and the second display area. A scanning direction of the first display area is such that scanning is conducted from the side that the sub pixel electrode of one of the sub-pixels of the first display area is located toward the side that the main pixel electrode of the one of the sub-pixels is located. A scanning direction of the second display area is opposite to the scanning direction of the first display area.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: June 2, 2020
    Inventor: Qiming Gan
  • Patent number: 10672888
    Abstract: Embodiments of the invention form a channel fin across from a major surface of a substrate, wherein a top surface of the channel fin extends substantially horizontally with respect to the major surface. A gate is formed across from the major surface and along a sidewall surface of the channel fin, wherein a first top surface of the gate is above the top surface of the channel fin and extends substantially horizontally with respect to the major surface. A second top surface of the gate is defined by a trench formed through an exposed sidewall portion of the gate in a direction that is substantially horizontal with respect to the major surface, wherein a gate length dimension of the initial gate is defined by a distance from a bottom surface of the gate to the second top surface of the gate.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: June 2, 2020
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10665779
    Abstract: Methods for additive formation of a STT-MRAM metal stack using a deposition process through a pre-patterned template that skims away metal ions that are less likely to enable anisotropic deposition on a substrate. The pre-patterned template is formed from a film stack using patterning techniques to form an opening in the film stack that exposes portions of an underlying substrate where a MTJ will be formed for an MRAM cell. The film stack cavity may be exposed to etch processes that selectively pull back the sidewall, such that other layers in the film stack protrude into the cavity. Additional treatments to the other layers may alter the opening sizes in the other layers. Metal deposited through the cavity such that metal ions with anisotropic characteristics will be skimmed away before reaching the substrate.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 26, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Noel Russell, Jeffrey Smith
  • Patent number: 10658263
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
  • Patent number: 10658366
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: May 19, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Liang Liao, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Wang Zhan
  • Patent number: 10658226
    Abstract: A method for preparing an SOI wafer by using rapid thermal processing includes: taking a silicon wafer as a raw material, sequentially performing process steps of oxidation, H+ implantation and bonding to obtain a bonded wafer with an H+ implantation layer; and then splitting the bonded wafer by using rapid thermal processing and microwaves to obtain a required SOI wafer. In the present invention, an SOI film after wafer splitting has better thickness uniformity and lower roughness. The present invention may improve lattice damage after implantation and reduce SOI surface defects after wafer splitting and thus improve the SOI surface quality. The present invention is high in wafer-splitting speed and thus reduces silicon wafer contamination. The present invention has high efficiency and an excellent comprehensive technical effect.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: May 19, 2020
    Assignee: Shenyang Silicon Technology Co., Ltd.
    Inventor: Jie Li
  • Patent number: 10651038
    Abstract: A semiconductor device includes: a semiconductor layer of silicon carbide including a plurality of layers disposed on a main surface side; an electrode layer that is one of the plurality of layers, wherein the electrode layer has an electrode connecting surface to which a conductive connecting member is connected, and the electrode layer is composed mainly of silver; and a first metal layer that is a layer, different from the electrode layer, among the plurality of layers, wherein the first metal layer has a first bonding surface bonded onto the electrode layer such that the electrode connecting surface is exposed to an outside, and a second bonding surface electrically connected to the semiconductor layer, and the first metal layer is composed mainly of titanium carbide.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: May 12, 2020
    Inventor: Yusuke Fukuda
  • Patent number: 10651194
    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: May 12, 2020
    Inventors: Ji Hoon Choi, Sung Gil Kim, Seulye Kim, Jung Ho Kim, Hong Suk Kim, Phil Ouk Nam, Jae Young Ahn, Han Jin Lim
  • Patent number: 10644257
    Abstract: A display device is provided including a display region arranged with a plurality of pixels, and a first sealing region arranged in an exterior periphery part of the display region, the display region includes an individual pixel electrode arranged in each of the plurality of pixels, a common pixel electrode arranged in upper layer of the individual pixel electrode and in succession to the plurality of pixels, and a light emitting layer arranged between the individual pixel electrode and the common pixel electrode, and the first sealing region includes a sealing layer arranged on a lower layer than the common pixel electrode and a region stacked with the common pixel electrode extending from the display region, the stacked region being enclosed by the display region.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 5, 2020
    Assignee: Japan Display Inc.
    Inventor: Jun Hanari
  • Patent number: 10615345
    Abstract: Measurements on organic single crystals reveal remarkable optical and electrical characteristics compared to disordered films but practical device applications require uniform, pinhole-free films. Disclosed herein is a process to reliably convert as-deposited amorphous thin films to ones that are highly crystalline, with grains on the order of hundreds of microns. The disclosed method results in films that are pinhole-free and that possess grains that individually are single crystal domains.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: April 7, 2020
    Inventors: Barry P. Rand, Michael A. Fusella, Siyu Yang
  • Patent number: 10615204
    Abstract: A solid-state image pickup device includes a semiconductor substrate in which photoelectric conversion units are arranged. An insulator is disposed on the semiconductor substrate. The insulator has holes associated with the respective photoelectric conversion units. Members are arranged in the respective holes. A light-shielding member is disposed on the opposite side of one of the members from the semiconductor substrate, such that only the associated photoelectric conversion unit is shielded from light. In the solid-state image pickup device, the holes are simultaneously formed and the members are simultaneously formed.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: April 7, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mineo Shimotsusa, Masahiro Kobayashi
  • Patent number: 10600852
    Abstract: Provided are an organic light-emitting display apparatus and a method of manufacturing the same. The organic light-emitting display apparatus includes: a substrate on which a display area is defined, wherein an image is displayed on the display area; a thin film transistor arranged on the display area of the substrate; a via-insulating layer covering the thin film transistor; a pixel electrode arranged on the via-insulating layer and electrically connected to the thin film transistor; a pixel-defining layer including an opening exposing a central portion of the pixel electrode, and covering an edge of the pixel electrode; a counter electrode facing the pixel electrode; an organic emission layer arranged between the pixel electrode and the counter electrode; a wire arranged on the via-insulating layer to be spaced apart from the pixel electrode and including a spacer area and a non-spacer area; and a spacer arranged on the spacer area.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 24, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jungkyu Lee, Taehyun Kim, Seungmin Lee, Sangho Park, Joosun Yoon
  • Patent number: 10600810
    Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Patrick Morrow, Stephen M. Cea, Rishabh Mehandru, Cory E. Weber
  • Patent number: 10593813
    Abstract: A new semiconductor rectifier structure. In general, a MOS-transistor-like structure is located above a JFET-like deeper structure. The present application teaches ways to combine and optimize these two structures in a merged device so that the resulting combined structure achieves both a low forward voltage and a high reverse breakdown voltage in a relatively small area. In one class of innovative implementations, an insulated (or partially insulated) trench is used to define a vertical channel in a body region along the sidewall of a trench, so that majority carriers from a “source” region (typically n+) can flow through the channel. An added “pocket” diffusion, of the same conductivity type as the body region (p-type in this example), provides an intermediate region around the bottom of the trench. This intermediate diffusion, and an additional deep region of the same conductivity type, define a deep JFET-like device which is in series with the MOS channel portion of the diode.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 17, 2020
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Richard A. Blanchard, Mohamed N. Darwish, Jun Zeng