Patents Examined by Wasiul Haider
  • Patent number: 12224279
    Abstract: A protection device may include a semiconductor substrate and a thyristor-type device, formed within the semiconductor substrate, where the thyristor device extends from a first main surface of the semiconductor substrate to a second main surface of the semiconductor substrate. The protection device may include a first PN diode, formed within the semiconductor substrate; and a second PN diode, formed within the semiconductor substrate, wherein the thyristor-type device is arranged in electrical series between the first PN diode and the second PN diode.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: February 11, 2025
    Assignee: Littelfuse Semiconductor (Wuxi) Co., Ltd.
    Inventors: Tsung-Wen Mou, Lei Shi, Jifeng Zhou
  • Patent number: 12218123
    Abstract: The present disclosure provides a chip part. The chip part includes a substrate, a first external electrode, a second external electrode, a capacitor portion, a lower electrode, a capacitive film and an upper electrode. The first external electrode and the second external electrode are disposed on a first main surface of the substrate. The capacitor portion is disposed on the first main surface of the substrate. The lower electrode includes a first body portion and a first peripheral portion integrally drawn out around the capacitor portion from the first body portion. The capacitive film includes a second body portion disposed within the capacitor portion and a second peripheral portion integrally drawn out from the second body portion to the first peripheral portion. The upper electrode is disposed on the capacitive film.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: February 4, 2025
    Assignee: ROHM CO., LTD.
    Inventor: Keisuke Fukae
  • Patent number: 12218182
    Abstract: Embodiments of the present invention provide a semiconductor device capable of improving current leakage property and a method for fabricating the same. According to an embodiment of the present invention, a capacitor comprises: a lower electrode; a dielectric layer over the lower electrode; and an upper electrode over the dielectric layer, the upper electrode including a conductive carbon-containing layer, wherein a carbon content in the conductive carbon-containing layer is more than 5 at % and equal to or less than 10 at %.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: February 4, 2025
    Assignee: SK hynix Inc.
    Inventors: Kwan Woo Do, Wan Joo Maeng, Jeong Yeop Lee, Ki Vin Im
  • Patent number: 12218190
    Abstract: A method of manufacturing an integrated circuit includes forming first and second false collector regions of a first conductivity type adjacent to a surface of an epitaxial layer of semiconductor material. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer and has a second conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: February 4, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alexei Sadovnikov, Guruvayurappan S. Mathur
  • Patent number: 12218191
    Abstract: A semiconductor structure includes a silicon carbide layer, which has a unit region and a termination region surrounding the unit region. A first guard ring structure is located in the termination region of the silicon carbide layer, and adjoins a top surface of the silicon carbide layer. The first guard ring structure may include at least one first guard ring well region. A second guard ring structure is located in the silicon carbide layer and below the first guard ring structure. The second guard ring structure may include at least one second guard ring well region, which corresponds to the at least one first guard ring well region in a vertical direction. A method for manufacturing the semiconductor structure is also provided.
    Type: Grant
    Filed: March 13, 2024
    Date of Patent: February 4, 2025
    Assignee: Diodes Incorporated
    Inventors: Ching-Wen Wang, Jie Li, Ming-Wei Tsai, Chiao-Shun Chuang
  • Patent number: 12218173
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu Wei, Yen-Liang Lin, Kuo-Cheng Lee, Hsun-Ying Huang, Hsin-Chi Chen
  • Patent number: 12206017
    Abstract: An electrostatic protection element including: a first impurity layer of second conductivity type formed on a semiconductor substrate of first conductivity type; a second impurity layer of the first conductivity type formed within the first impurity layer; a first contact layer of the first conductivity type formed in a region within the first impurity layer other than at the second impurity layer; a second and a third contact layer both of the second conductivity type and formed within the second impurity layer; and multilayer wiring connected through a stack structure to the first, the second, and the third contact layer, wherein the stack structure includes at least a first layer wiring connected to each of the first, the second, and the third contact layer, and a second layer wiring connected to the first layer wiring directly above each of the first, the second, and the third contact layer.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: January 21, 2025
    Assignee: KABUSHIKI KAISHA TOKAI-RIKA-DENKI-SEISAKUSHO.
    Inventors: Kengo Shima, Kazuya Adachi
  • Patent number: 12206019
    Abstract: According to one embodiment, a semiconductor device includes a substrate having a first surface and an insulator that surrounds a first region of the first surface. A gate electrode is on the first region and has a first resistivity. A first conductor is also on the first region. The first conductor comprises a same material as the gate electrode, but has a second resistivity that is different from the first resistivity. The resistivity may be different, for example, by either use of different dopants/impurities or different concentrations of dopants/impurities. Resistivity may also be different due to inclusion of a metal silicide on the conductors or not.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: January 21, 2025
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Kanako Komatsu
  • Patent number: 12193235
    Abstract: A nonvolatile memory device includes a channel layer, a plurality of gate electrodes and a plurality of separation layers spaced apart from the channel layer and alternately arranged, a charge trap layer between the gate electrodes in the channel layer, and a charge blocking layer between the charge trap layer and the gate electrode.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: January 7, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngtek Oh, Hyeyoung Kwon, Taein Kim, Gukhyon Yon, Minhyun Lee
  • Patent number: 12191362
    Abstract: Problem: To reduce the likelihood of insufficient electrical continuity in wiring in a semiconductor device.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: January 7, 2025
    Assignee: AOI Electronics Co., Ltd
    Inventor: Takashi Suzuki
  • Patent number: 12191436
    Abstract: An emitter and a method for emitting light are described. The emitter has a substrate with a substrate surface and at least one LED element arranged on the substrate surface for generating the light to be emitted. An active cooling unit for cooling the at least one LED element has at least one cooling channel. The at least one cooling channel is arranged on the substrate surface in a beam path of at least one portion of the light to be emitted, which can be generated by means of the at least one LED element, for redirecting the light to be emitted.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: January 7, 2025
    Assignee: WURTH ELEKTRONIK EISOS GMBH & CO. KG
    Inventors: Zhelio Andreev, Marcel Dörr
  • Patent number: 12191351
    Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming same. The structure comprises a semiconductor substrate including a trench, a source and a drain in the semiconductor substrate, a dielectric layer inside the trench, and a gate in the dielectric layer. The trench has a first sidewall and a second sidewall, the source is adjacent to the first sidewall of the trench, the drain is adjacent to the second sidewall of the trench, and the gate is laterally between the first sidewall of the trench and the second sidewall of the trench. The structure further comprises an air gap in the dielectric layer. The air gap is below the gate, and the air gap is laterally between the first sidewall of the trench and the second sidewall of the trench.
    Type: Grant
    Filed: May 14, 2024
    Date of Patent: January 7, 2025
    Assignee: GlobalFoundries Singapore Pte. Ltd.
    Inventors: Bong Woong Mun, Jeffrey B. Johnson
  • Patent number: 12183730
    Abstract: A silicon-controlled rectifier includes a semiconductor body including a first main surface, an active device region, a first, a second, a third and a fourth surface contact area at the first main surface and arranged directly one after another along a first lateral direction, wherein the semiconductor body is electrically contacted at each of the first to fourth surface contact areas, and a first, a second, a third and a fourth SCR region, wherein the first and third SCR regions are of a first conductivity type and directly adjoin the first and third surface contact areas, respectively, and wherein the second and fourth SCR regions are of a second conductivity type and directly adjoin the second and fourth surface contact areas, respectively, wherein the first SCR region is electrically connected to the fourth SCR region, and the second SCR region is electrically connected to the third SCR region.
    Type: Grant
    Filed: November 28, 2023
    Date of Patent: December 31, 2024
    Assignee: Infineon Technologies AG
    Inventors: Christian Cornelius Russ, Gabriel-Dumitru Cretu, Filippo Magrini
  • Patent number: 12183720
    Abstract: Solid-state lighting devices including light-emitting diodes (LEDs), and more particularly LED packages are disclosed. Arrangements for LED packages are disclosed that provide improved reliability and improved emission characteristics in a variety of applications, including outdoor LED displays as well as general illumination. LED packages are disclosed with linear arrangements of LED chips and corresponding lenses to provide improved visibility and color mixing at higher viewing angles. LED packages are disclosed that include different types of lenses that are arranged within the same LED package depending on desired emission characteristics. Body structures for LED packages are disclosed that include arrangements for improved adhesion with encapsulant materials and optional potting materials to provide improved moisture barriers.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: December 31, 2024
    Assignee: CreeLED, Inc.
    Inventors: Chak Hau Pang, JuZuo Sheng, Yue Kwong Lau, Zhenyu Zhong
  • Patent number: 12183647
    Abstract: The present invention provides a semiconductor device including an insulating layer, a conductive layer bonded to one main surface of the insulating layer, a semiconductor element arranged such that the upper surface of the semiconductor element faces a direction same as the one main surface of the insulating layer, an upper electrode provided on the upper surface of the semiconductor element, a wiring member that has one end electrically bonded to the upper electrode of the semiconductor element and has another end electrically bonded to the conductive layer, and has a hollow portion, a first sealing material, and a second sealing material, in which the first sealing material seals at least part of the semiconductor element so as to be in contact with the semiconductor element, and the second sealing material seals the wiring member so as to be in contact with the wiring member.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: December 31, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Soichi Sakamoto, Junji Fujino, Hiroshi Kawashima, Taketoshi Maeda
  • Patent number: 12185616
    Abstract: An electronic device may include a display and an optical sensor formed underneath the display. The display may have both a full pixel density region and a pixel removal region with a plurality of high-transmittance areas that overlap the optical sensor. To mitigate reflectance mismatch between the full pixel density region and the pixel removal region, the pixel removal region may include a transition region at one or more edges. In the transition region, one or more components may have a gradual density change between the full pixel density region and a central portion of the pixel removal region. Components that may have a changing density in the transition region include dummy thin-film transistor sub-pixels, dummy anodes, a cathode layer, and a touch sensor metal layer. The transition region may also include anodes that gradually change shape and/or size.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: December 31, 2024
    Assignee: Apple Inc.
    Inventors: Ricardo A Peterson, Yuchi Che, Warren S Rieutort-Louis, Abbas Jamshidi Roudbari, Yi Qiao, Yue Cui, Jean-Pierre S Guillou, Shyuan Yang, Tsung-Ting Tsai
  • Patent number: 12183677
    Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: December 31, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hun Lee, Seokjung Yun, Chang-Sup Lee, Seong Soon Cho, Jeehoon Han
  • Patent number: 12185529
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a buried gate structure positioned in the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the buried gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: December 31, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Wei-Zhong Li, Hsih-Yang Chiu
  • Patent number: 12176341
    Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.
    Type: Grant
    Filed: November 18, 2023
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao-Yi Hung, Wun-Jie Lin, Jam-Wem Lee, Kuo-Ji Chen
  • Patent number: 12170311
    Abstract: A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer comprising a body ring structure, forming a source and a body region in the epitaxial layer, forming an interlayer dielectric layer over the epitaxial layer, forming a gate-source Electrostatic Discharge (ESD) diode structure in the interlayer dielectric layer, forming a source contact connected to the source, and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, and forming a drain contact underneath the substrate.
    Type: Grant
    Filed: July 2, 2024
    Date of Patent: December 17, 2024
    Assignee: Diodes Incorporated
    Inventors: Wan-Yu Kai, Chia-Wei Hu, Ta-Chuan Kuo