Patents Examined by Wasiul Haider
  • Patent number: 10586837
    Abstract: The present invention provides an array substrate, a method for manufacturing the same and a display device. The array substrate includes a substrate; a anode layer and a pixel defining layer on the substrate; an auxiliary cathode layer on the pixel defining layer; a spacer layer on the auxiliary cathode layer; an organic light-emitting layer covering the anode layer, the pixel defining layer, and the spacer layer; a cathode layer covering the organic light-emitting layer, wherein the cathode layer laps with the auxiliary cathode layer on the pixel defining layer. Since the auxiliary cathode layer disposed on the pixel defining layer corresponds to the non-display area, the material with low resistivity can be selected for the auxiliary cathode layer. Thus the uniformity of the display brightness and the like of the screen can be improved, thereby improving the display quality of the screen.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: March 10, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xinwei Gao
  • Patent number: 10580808
    Abstract: A photodetection device includes: a photoelectric converter generating charge; a first diffusion region having a first end connected to the photoelectric converter and a second end and extending in a first direction from the first end toward the second end; a second diffusion region having a third end connected to a first side surface, of the first diffusion region, which is along the first direction and a fourth end and extending in a second direction from the third end toward the fourth end; a first charge accumulator connected to the fourth end; a first gate electrode covering at least part of the first diffusion region; and a second gate electrode covering at least part of the second diffusion region. The second gate electrode covers a first portion of the first diffusion region without the first gate electrode intervention. The first portion is adjacent to the second diffusion region.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: March 3, 2020
    Assignee: Panasonic Intellectual Property Management Co. Ltd.
    Inventors: Masayuki Takase, Sanshiro Shishido
  • Patent number: 10553540
    Abstract: A fabric-based item may include fabric layers and other layers of material. An array of electrical components may be mounted in the fabric-based item. The electrical components may be mounted to a support structure such as a flexible printed circuit. The flexible printed circuit may have a mesh shape formed from an array of openings. Serpentine flexible printed circuit segments may extend between the openings. The electrical components may be light-emitting diodes or other electrical devices. Polymer with light-scattering particles or other materials may cover the electrical components. The flexible printed circuit may be laminated between fabric layers or other layers of material in the fabric-based item.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: February 4, 2020
    Assignee: Apple Inc.
    Inventors: Daniel D. Sunshine, Paul S. Drzaic, Daniel A. Podhajny, David M. Kindlon, Hoon Sik Kim, Kathryn P. Crews, Yung-Yu Hsu
  • Patent number: 10546952
    Abstract: The present invention provides a method of manufacturing a semiconductor device to improve the manufacturing yield of the semiconductor device. The manufacturing method includes the steps of: forming a groove extending in a first direction (y direction) across a first power transistor formation region and a second power transistor formation region, in a back surface of a semiconductor wafer; filling the groove with a conductor film by forming the conductor film on the back surface in which the groove is formed; and exposing the back surface of the semiconductor wafer by removing a portion of the conductor film.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: January 28, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Tetsuji Togami
  • Patent number: 10541260
    Abstract: An organic photoelectric conversion element includes an anode, a cathode, and a photoelectric conversion portion between the anode and the cathode. The photoelectric conversion portion includes a first organic compound layer containing an organic compound. Also, a second organic compound layer is disposed between the cathode and the photoelectric conversion portion. The second organic compound layer contains an organic compound having an ionization potential of 5.1 eV or less and a band gap of 2.5 eV or more.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: January 21, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Jun Kamatani, Naoki Yamada, Masumi Itabashi, Yosuke Nishide, Hirokazu Miyashita, Tetsuya Kosuge, Satoru Shiobara, Tetsuo Takahashi, Akihiro Senoo, Kentaro Ito, Satoshi Ota
  • Patent number: 10539528
    Abstract: Methods and devices for a stacked nanofluidic sensor are described. The stacked nanofluidic sensor and methods for forming a nanosheet stack of at least two alternating layers of a first nanosheet material and a second nanosheet material on a substrate. Additionally, a gate structure is formed on the nanosheet stack. Further, nanofluidic channels are formed within the gate structure, including removing each layer of the first nanosheet material within the gate structure to form a channel configured to receive a nanofluidic sample.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kangguo Cheng
  • Patent number: 10529899
    Abstract: Disclosed are a phosphor sheet capable of improving color purity of each of RGB reproduced through a color filter, a white light source device including the phosphor sheet, and a display device including the white light source device. The disclosed phosphor sheet is a phosphor sheet for converting LED light into white light, including: a phosphor layer containing at least a phosphor and a resin; and a pair of transparent substrates sandwiching the phosphor layer, in which the phosphor sheet includes a coloring material having an absorption maximum wavelength of at least one of from 480 nm to 510 nm or from 570 nm to 620 nm.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: January 7, 2020
    Assignee: Dexerials Corporation
    Inventors: Noritaka Sato, Koichi Kishimoto, Tomomitsu Hori, Yasushi Ito
  • Patent number: 10522671
    Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Po-Chih Chen, Jiun-Lei Yu, Yao-Chung Chang, Chun-Lin Tsai
  • Patent number: 10522447
    Abstract: Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 31, 2019
    Assignee: Infineon Technologies AG
    Inventor: Georg Meyer-Berg
  • Patent number: 10515897
    Abstract: A semiconductor structure includes a semiconductor device, an overlying silicon nitride diffusion barrier layer, and an interconnect structure extending through the silicon nitride diffusion barrier layer. The interconnect structure includes a titanium diffusion barrier structure in contact with the silicon nitride diffusion barrier layer to form a continuous hydrogen diffusion barrier structure.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 24, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Akio Nishida, Murshed Chowdhury, Takahito Fujita, Kiyokazu Shishido, Hiroyuki Ogawa
  • Patent number: 10497642
    Abstract: The present disclosure relates to an integrated power semiconductor packaging apparatus and a power converter containing the integrated power semiconductor packaging apparatus. The integrated power semiconductor packaging apparatus comprises a plurality of power semiconductor devices and an electrically insulative substrate formed integrally. The electrically insulative substrate comprises a flat surface, at least one separation wall protruding from the flat surface and a flow channel inside the electrically insulative substrate. The at least one separation wall is configured to separate the flat surface into a plurality of flat areas, and each of the plurality of flat areas is configured to receive one of the plurality of power semiconductor devices. The flow channel is configured for allowing a coolant flowing through to remove heat from the plurality of power semiconductor devices.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 3, 2019
    Assignee: General Electric Company
    Inventors: Saijun Mao, Bo Qu, Jingkui Shi, He Xu, Jie Shen, Lin Lan, Rui Li, Zhihui Yuan, Alistair Martin Waddell, Stefan Schroeder, Marius Michael Mechlinski, Mark Aaron Chan
  • Patent number: 10490644
    Abstract: In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epitaxial layer disposed on the SiC substrate. The device can include a well region disposed in the epitaxial layer, a source region disposed in the well region and a gate trench disposed in the epitaxial layer and adjacent to the source region. The gate trench can have a depth that is greater than a depth of the well region and less than a depth of the epitaxial layer. The device can include a hybrid gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench. The hybrid gate dielectric can include a first high-k material and a second high-k dielectric material that is different than the first high-k dielectric material. The device can include a conductive gate electrode disposed on the hybrid gate dielectric.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: November 26, 2019
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Salman Akram, Venkat Ananthan
  • Patent number: 10490479
    Abstract: A semiconductor package includes an integrated circuit (IC), a heat dissipation structure, a molding layer and an antenna. The IC is mounted on a first surface of a first redistribution layer (RDL). The heat dissipation structure is mounted on a second surface of the first RDL. The molding compound is disposed over the first surface of the first RDL. The antenna is disposed on the second surface of the first RDL, wherein the antenna is disposed side-by-side to the heat dissipation structure.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Han-Ping Pu, Hsin-Yu Pan, Sen-Kuei Hsu
  • Patent number: 10475964
    Abstract: Provided is a method of producing an n-type ohmic electrode that can form a good ohmic contact with an n-type AlxGa1-xN (0.5?x?1) layer. The method of producing an n-type ohmic electrode includes: a first step of forming a first layer 11 made of one of Ti and Hf on a surface of a layer 30; a second step of forming a second layer 12 made of Sn on the surface of the first layer 11; a third step of forming a third layer 13 made of one of V and Mo on the surface of the second layer 12; a fourth step of forming a fourth layer 14 made of Al on the surface of the third layer 13; and a fifth step of performing heat treatment on the first layer 11, the second layer 12, the third layer 13, and the fourth layer 14.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: November 12, 2019
    Assignee: DOWA Electronics Materials Co., Ltd.
    Inventor: Tatsunori Toyota
  • Patent number: 10475813
    Abstract: In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region. The ferroelectric memory device includes a ferroelectric superlattice structure disposed on the substrate and having at least two kinds of different dielectric layers alternately stacked. Further, the ferroelectric memory device includes a gate electrode layer disposed on the superlattice structure.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 12, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyangkeun Yoo
  • Patent number: 10468523
    Abstract: A recessed portion is formed in a top surface of an isolation insulation film filling an isolation trench between a p+ source region and a p+ drain region. A p? drift region is located below the isolation trench and connected to the p+ drain region. A gate electrode fills the recessed portion. An n-type impurity region is located below the p? drift region and directly below the recessed portion.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 5, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroki Fujii, Takahiro Mori
  • Patent number: 10453972
    Abstract: An integrated optical sensor comprises a semiconductor substrate (1), an integrated circuit (2), a dielectric layer (6), a wiring (4), a structured filter layer (7) and a diffuser (10). The semiconductor substrate (1) has a main surface (11) and the integrated circuit (2) is arranged in the substrate (1) at or near the main surface (11). Furthermore, the integrated circuit (2) comprises at least one light sensitive component (3). The dielectric layer (6) comprises at least one compound of the semiconductor material. The dielectric layer (6) is arranged on or above the main surface (11). The wiring (4) is arranged in the dielectric layer (6) and provides an electrical connection to the integrated circuit (2), i.e. the wiring is connected to the integrated circuit (2). The structured filter layer (7) is arranged on the dielectric layer (6) and faces the at least one light sensitive component (3), i.e. the diffusor (10) is positioned over the structured filter layer (7).
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: October 22, 2019
    Assignee: ams AG
    Inventor: Hubert Enichlmair
  • Patent number: 10446605
    Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes: a substrate, a bonding metal layer, a reflective layer, a first conductive layer, an active layer, a second conductive layer, first electrode(s) and second electrode(s). The first electrode(s) extends, from one side of the bonding metal layer away from the substrate, to the first conductive layer, to be connected with the bonding metal layer and the first conductive layer. The second electrode(s) penetrates through the substrate and the bonding metal layer to be in contact with the reflective layer. The semiconductor device, forming a structure sharing the first conductive layer, has more uniform illumination and a higher light extraction rate, and eliminates interferences between pixel units, achieves better uniformity of emitted light wavelength and makes distribution of electric current flowing through different pixel units more even.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: October 15, 2019
    Assignee: Enkris Semiconductor, Inc.
    Inventor: Liyang Zhang
  • Patent number: 10438878
    Abstract: A package and method of making a package. In one example, the package includes an at least partially electrically conductive carrier, a passive component mounted on the carrier, and an at least partially electrically conductive connection structure electrically connecting the carrier with the component and comprising spacer particles configured for spacing the carrier with regard to the component.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: October 8, 2019
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schindler, Franz-Peter Kalz, Volker Strutz
  • Patent number: 10439049
    Abstract: A nanosheet transistor device having reduced access resistance is fabricated by recessing channel nanosheets and replacing the channel material with epitaxially grown doped extension regions. Sacrificial semiconductor layers between the channel nanosheets are selectively removed without damaging source/drain regions epitaxially grown on the extension regions. The sacrificial semiconductor layers are replaced by gate dielectric and gate metal layers.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Shogo Mochizuki, Alexander Reznicek