Patents Examined by Wasiul Haider
  • Patent number: 10475964
    Abstract: Provided is a method of producing an n-type ohmic electrode that can form a good ohmic contact with an n-type AlxGa1-xN (0.5?x?1) layer. The method of producing an n-type ohmic electrode includes: a first step of forming a first layer 11 made of one of Ti and Hf on a surface of a layer 30; a second step of forming a second layer 12 made of Sn on the surface of the first layer 11; a third step of forming a third layer 13 made of one of V and Mo on the surface of the second layer 12; a fourth step of forming a fourth layer 14 made of Al on the surface of the third layer 13; and a fifth step of performing heat treatment on the first layer 11, the second layer 12, the third layer 13, and the fourth layer 14.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: November 12, 2019
    Assignee: DOWA Electronics Materials Co., Ltd.
    Inventor: Tatsunori Toyota
  • Patent number: 10475813
    Abstract: In an embodiment, a ferroelectric memory device includes a substrate having a source region and a drain region. The ferroelectric memory device includes a ferroelectric superlattice structure disposed on the substrate and having at least two kinds of different dielectric layers alternately stacked. Further, the ferroelectric memory device includes a gate electrode layer disposed on the superlattice structure.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 12, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyangkeun Yoo
  • Patent number: 10468523
    Abstract: A recessed portion is formed in a top surface of an isolation insulation film filling an isolation trench between a p+ source region and a p+ drain region. A p? drift region is located below the isolation trench and connected to the p+ drain region. A gate electrode fills the recessed portion. An n-type impurity region is located below the p? drift region and directly below the recessed portion.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 5, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroki Fujii, Takahiro Mori
  • Patent number: 10453972
    Abstract: An integrated optical sensor comprises a semiconductor substrate (1), an integrated circuit (2), a dielectric layer (6), a wiring (4), a structured filter layer (7) and a diffuser (10). The semiconductor substrate (1) has a main surface (11) and the integrated circuit (2) is arranged in the substrate (1) at or near the main surface (11). Furthermore, the integrated circuit (2) comprises at least one light sensitive component (3). The dielectric layer (6) comprises at least one compound of the semiconductor material. The dielectric layer (6) is arranged on or above the main surface (11). The wiring (4) is arranged in the dielectric layer (6) and provides an electrical connection to the integrated circuit (2), i.e. the wiring is connected to the integrated circuit (2). The structured filter layer (7) is arranged on the dielectric layer (6) and faces the at least one light sensitive component (3), i.e. the diffusor (10) is positioned over the structured filter layer (7).
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: October 22, 2019
    Assignee: ams AG
    Inventor: Hubert Enichlmair
  • Patent number: 10446605
    Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes: a substrate, a bonding metal layer, a reflective layer, a first conductive layer, an active layer, a second conductive layer, first electrode(s) and second electrode(s). The first electrode(s) extends, from one side of the bonding metal layer away from the substrate, to the first conductive layer, to be connected with the bonding metal layer and the first conductive layer. The second electrode(s) penetrates through the substrate and the bonding metal layer to be in contact with the reflective layer. The semiconductor device, forming a structure sharing the first conductive layer, has more uniform illumination and a higher light extraction rate, and eliminates interferences between pixel units, achieves better uniformity of emitted light wavelength and makes distribution of electric current flowing through different pixel units more even.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: October 15, 2019
    Assignee: Enkris Semiconductor, Inc.
    Inventor: Liyang Zhang
  • Patent number: 10439049
    Abstract: A nanosheet transistor device having reduced access resistance is fabricated by recessing channel nanosheets and replacing the channel material with epitaxially grown doped extension regions. Sacrificial semiconductor layers between the channel nanosheets are selectively removed without damaging source/drain regions epitaxially grown on the extension regions. The sacrificial semiconductor layers are replaced by gate dielectric and gate metal layers.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10438878
    Abstract: A package and method of making a package. In one example, the package includes an at least partially electrically conductive carrier, a passive component mounted on the carrier, and an at least partially electrically conductive connection structure electrically connecting the carrier with the component and comprising spacer particles configured for spacing the carrier with regard to the component.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: October 8, 2019
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schindler, Franz-Peter Kalz, Volker Strutz
  • Patent number: 10431502
    Abstract: A method is presented for forming a transistor having reduced parasitic contact resistance. The method includes forming a first device over a semiconductor structure, forming a second device adjacent the first device, forming an ILD over the first and second devices, and forming recesses within the ILD to expose the source/drain regions of the first device and the source/drain regions of the second device. The method further includes forming a first dielectric layer over the ILD and the top surfaces of the source/drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source/drain regions of the second device resulting in second dielectric layers formed over the source/drain regions of the second device, and forming an epitaxial layer over the source/drain regions of the first device after removing remaining portions of the first dielectric layer.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Shogo Mochizuki, Chun Wing Yeung, Hemanth Jagannathan
  • Patent number: 10431627
    Abstract: A magnetic memory device is provided including a magnetic tunnel junction pattern having a free pattern, a reference pattern, and a tunnel barrier pattern between the free pattern and the reference pattern. The free pattern includes a first sub-free pattern, a second sub-free pattern, and a third sub-free pattern. The first sub-free pattern is between the tunnel barrier pattern and the third sub-free pattern, and the second sub-free pattern is between the first sub-free pattern and the third sub-free pattern. The second sub-free pattern includes nickel-cobalt-iron-boron (NiCoFeB), and the third sub-free pattern includes nickel-iron-boron (NiFeB). Related methods of fabrication are also provided.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hoon Kim, Juhyun Kim
  • Patent number: 10418578
    Abstract: This disclosure provides a quantum dot light-emitting diode comprising a first electron layer, an organic light-emitting layer, a first hole layer, a second electron layer, a quantum dot light-emitting layer, and a second hole layer. The first electron layer and the first hole layer are configured to transport first electrons and first holes to the organic light-emitting layer. The organic light-emitting layer is configured to emit a first light by recombining the first electrons and the first holes. The second electron layer and the second hole layer are configured to transport second electrons and second holes to the quantum dot light-emitting layer. The quantum dot light-emitting layer is configured to emit a second light by recombining the second electrons and the second holes.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: September 17, 2019
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Wei Yuan, Shibo Jiao
  • Patent number: 10418522
    Abstract: An optoelectronic device and method of manufacturing an optoelectronic device are disclosed. The optoelectronic device includes a substrate; a semiconductor comprising an n-type layer disposed on the substrate, a p-type layer disposed on the n-type layer, and an active layer disposed between the n-type layer and the p-type layer; a transition layer disposed on the substrate and located between the n-type layer and the substrate, the transition layer including an oxygenated IIIA-transition metal nitride; and a p-contact layer disposed on the p-type layer of the semiconductor.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 17, 2019
    Assignee: GOFORWARD TECHNOLOGY INC.
    Inventors: Yangang Xi, Jiguang Li
  • Patent number: 10411100
    Abstract: A semiconductor structure including a substrate, a dielectric layer and a polysilicon layer is provided. The dielectric layer is disposed on the substrate. The polysilicon layer is disposed on the dielectric layer. A fluorine dopant concentration in the polysilicon layer presents Gaussian distributions from a top portion to a bottom portion of the polysilicon layer. Fluorine dopant peak concentrations of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: September 10, 2019
    Assignee: United Microelectronics Corp.
    Inventor: Chen-Wei Pan
  • Patent number: 10410964
    Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Kanta Saino
  • Patent number: 10396039
    Abstract: A lead frame includes: a second terminal that is disposed to surround terminals on a package plane and can be grounded; and a conductive member that covers molded resin and is electrically connected to the second terminal.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: August 27, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroyuki Mizutani, Hidenori Ishibashi, Hideharu Yoshioka, Kiyoshi Ishida
  • Patent number: 10396181
    Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
  • Patent number: 10388817
    Abstract: An optical transducer system that has a light source and a transducer. The light source generates light that has a predetermined photon energy. The transducer has a bandgap energy that is smaller than the photon energy. An increased optical to electrical conversion efficiency is obtained by illuminating the transducer at increased optical power densities. A method of converting optical energy to electrical energy is also provided.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 20, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Simon Fafard, Denis Paul Masson
  • Patent number: 10381330
    Abstract: A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: August 13, 2019
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Justin Hiroki Sato, Bomy Chen, Walter Lundy
  • Patent number: 10374012
    Abstract: Provided herein may be an electronic device including a semiconductor memory. The semiconductor memory may include: first column lines and sub-column lines extending in a first direction; first row lines extending in a second direction; first tiles including first memory cells connected between the first column lines and the first row lines; first contact plugs coupled to the sub-column lines and disposed between the first tiles in the first direction; second contact plugs coupled to the first row lines and disposed between the first tiles in the second direction; and a first connection structure partially coupling the first column lines to the sub-column lines such that the longer a current path on a first row line from a selected first memory cell to the corresponding second contact plug, the shorter a current path from the selected first memory cell to the corresponding first contact plug.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: August 6, 2019
    Assignee: SK HYNIX INC.
    Inventor: Dong Hoon Kim
  • Patent number: 10373986
    Abstract: An array substrate, a display panel and a display device, including at least two gate lines in a display area, a gate driving circuit and at least two gate fan-out lines in a non-display are described. One end of each of the gate fan-out lines are electrically connected with one signal output of the gate driving circuit and the other end of each of the gate fan-out lines are electrically connected with the gate lines. By configuring a first gate fan-out line of the gate fan-out lines and the gate driving circuit to have an overlapping area outside a mutual connection area, an area where the gate fan-out lines are overlaps the gate driving circuit, space occupied by the first gate fan-out line outside the gate driving circuit is decreased to shorten a distance between the gate driving circuit and the display area.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: August 6, 2019
    Assignee: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Guochang Lai, Junyi Li, Zhongjie Zhang
  • Patent number: 10354876
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate and a material layer. The substrate has a first region, and the material layer is disposed on the substrate. The material layer includes plural of first patterns and plural of second patterns arranged in an array, and two third patterns. The first patterns are disposed within the first region, the second patterns are disposed at two opposite outer sides of the first region, and the third patterns are disposed at another two opposite outer sides of the first region, wherein each of the third patterns partially merges each of a part of the first patterns and each of a part of the second patterns.
    Type: Grant
    Filed: June 24, 2018
    Date of Patent: July 16, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Yu-Cheng Tung, Fu-Che Lee, Ying-Chih Lin