Abstract: A light emitting device according to an embodiment includes a body having a recess; a light emitting chip disposed in the recess; and a first dampproof layer sealing the light emitting chip and extended from a surface of the light emitting chip to a bottom of the recess, wherein the light emitting chip includes a wavelength range of 100 nm to 280 nm, and the first dampproof layer includes a fluororesin-based material.

Abstract: A device including a transistor is fabricated by forming a first part of a first region of the transistor through the implantation of dopants through a first opening. The second region of the transistor is then formed in the first opening by epitaxy.

Abstract: The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure provides a semiconductor device including an isolation region disposed on a substrate, a pair of diffusion structures disposed upon the isolation region, a dielectric layer that covers side surfaces of the diffusion structures, and a gate structure disposed on the dielectric layer and between the diffusion structures, where the gate structure is electrically coupled to the diffusion structures.

Abstract: To provide a semiconductor device with favorable electrical characteristics. To provide a method for manufacturing a semiconductor device with high productivity. To reduce the temperatures in a manufacturing process of a semiconductor device. An island-like oxide semiconductor layer is formed over a first insulating film; a second insulating film and a first conductive film are formed in this order, covering the oxide semiconductor layer; oxygen is supplied to the second insulating film through the first conductive film; a metal oxide film is formed over the second insulating film in an atmosphere containing oxygen; a first gate electrode is formed by processing the metal oxide film; a third insulating film is formed, covering the first gate electrode and the second insulating film; and first heat treatment is performed. The second insulating film and the third insulating film each include oxide. The highest temperature in the above steps is 340° C. or lower.

Abstract: One illustrative device disclosed herein includes a semiconductor substrate and a bipolar junction transistor (BJT) device that comprises a collector region, a base region and an emitter region. In this example, the device also includes a field effect transistor and at least one base conductive contact structure that conductively and physically contacts the base region.

Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.

Abstract: Embodiments include a first set of fins having an emitter of a bipolar junction transistor (BJT) disposed over the first set of fins, a second set of fins having a base of the BJT disposed over the second set of fins, and a third set of fins having a collector of the BJT disposed over the third set of fins. A first gate structure is disposed over the first set of fins adjacent to the emitter. A second gate structure is disposed over the second set of fins adjacent to the base. A third gate structure is disposed over the third set of fins adjacent to the collector. The first gate structure, second gate structure, and third gate structure are physically and electrically separated.

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.

Abstract: A display device includes: a substrate; a thin film transistor on the substrate; a first electrode, a light emitting diode and a second electrode sequentially on the thin film transistor; a barrier layer on the second electrode, the barrier layer including at least one organic layer; and a front film on the barrier layer, wherein the at least one organic layer includes a chemically self-healing material.

Abstract: A display device includes: a substrate including a display area, a peripheral area, a pad area, and a bending area disposed between the display area and the pad area, wherein the peripheral area is disposed outside the display area, and the pad area is disposed in the peripheral area; a plurality of metallic wirings positioned on the substrate and in the bending area; a first organic insulating layer and a second organic insulating layer stacked on the plurality of metallic wirings in the bending area; and a first dummy metallic pattern disposed between the first organic insulating layer and the second organic insulating layer.

Abstract: A tunneling field effect transistor according to an embodiment of the present invention includes: a first semiconductor layer having a first conductive type; a second semiconductor layer having a second conductive type and realizing a heterojunction with respect to the first semiconductor layer in a first region; a gate insulating layer over the second semiconductor layer in the first region; a gate electrode layer over the gate insulating layer; a first electrode layer electrically connected to the first semiconductor layer; a second electrode layer electrically connected to the second semiconductor layer; and a first insulating layer interposed between the first semiconductor layer and the second semiconductor layer in a second region adjacent to the first region toward the second electrode layer.

Abstract: A semiconductor device includes an integrated trench capacitor in a substrate, with a field oxide layer on the substrate. The trench capacitor includes trenches extending into semiconductor material of the substrate, and a capacitor dielectric in the trenches on the semiconductor material. The trench capacitor further includes an electrically conductive trench-fill material on the capacitor dielectric. A portion of the capacitor dielectric extends into the field oxide layer, between a first segment of the field oxide layer over the trench-fill material and a second segment of the field oxide layer over the semiconductor material. The integrated trench capacitor has a trench contact to the trench-fill material in each of the trenches, and substrate contacts to the semiconductor material around the trenches, with no substrate contacts between the trenches.

Abstract: An n-type semiconductor layer has a single-crystal structure and is made of a wide-gap semiconducting material. A p-type semiconductor layer is provided on the n-type semiconductor layer and made of a material different from the aforementioned wide-gap semiconducting material, and has either a microcrystalline structure or an amorphous structure. An electrode is provided on at least one of the n-type semiconductor layer and the p-type semiconductor layer.

Abstract: A chip mounting structure and a chip mounting device are provided. The chip mounting structure includes a circuit substrate and a plurality of micro heaters. The circuit substrate has a plurality of solder pads. A plurality of micro heaters are disposed on the circuit substrate adjacent to the solder pad. The plurality of chips are disposed on the circuit substrate, and the chip is electrically connected to the solder pad by a solder ball. Therefore, the soldering yield of the process can be reduced by the chip mounting structure and the chip mounting device.

Abstract: The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed.

Abstract: The present invention provides an ESD protection device with the mechanism of punch through to achieve low trigger voltage. At the same time, the structure of ESD protection device includes parasitic NPN and parasitic PNP. Parasitic NPN and parasitic PNP will form a silicon controlled rectifier (SCR) device with snapback behavior to increase the protection capability of ESD protection device.

Abstract: The present disclosure provides a semiconductor device comprising a substrate; a first III-V compound layer over the substrate; a second III-V compound layer on the first III-V compound layer; a third III-V compound layer on the second III-V compound layer; a source region on the third III-V compound layer; a drain region on the third III-V compound layer; a first dielectric layer arranged on the second III-V compound layer through the third III-V compound layer; and a gate region on the first dielectric layer, wherein a bottom of the gate region is higher than a top surface of the first dielectric layer; the second lateral distance is larger than the first lateral distance.

Abstract: A transient voltage suppression device including a substrate of a first conductivity type, a first well of a second conductivity type, a first anode, a first cathode, and a first trigger node is provided. The first well is disposed in the substrate. The first anode is disposed in the substrate outside the first well and includes a second doped region of the second conductivity type and a third doped region of the first conductivity type disposed between the second doped region and the first doped region. The first trigger node is disposed between the first anode and the first cathode, and includes a fourth region of the first conductivity type disposed in the substrate and a fifth doped region of the second conductivity type at least partially disposed in the first well and disposed between the fourth doped region and the third doped region.

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

Abstract: A semiconductor device comprising an N-type metal oxide semiconductor (NMOS) gate-all-around (GAA) transistor and a P-type metal oxide semiconductor (PMOS) GAA transistor with high charge mobility channel materials is disclosed. The semiconductor device may include a substrate. The semiconductor device may also include an NMOS GAA transistor on the substrate, wherein the NMOS GAA transistor comprises a first channel material. The semiconductor device may further include a PMOS GAA transistor on the substrate, wherein the PMOS GAA transistor comprises a second channel material. The first channel material may have an electron mobility greater than an electron mobility of Silicon (Si) and the second channel material may have a hole mobility greater than a hole mobility of Si.