Abstract: To provide a light emitting device that is compact and has high efficiency of extracting light comprising a support body that incorporates a light emitting element. The light emitting device has the protective element 106 mounted on the electrically conductive member 103a and the base 105 mounted on the electrically conductive member 103a, while at least part of the protective element 106 is covered with the base 105, and the light emitting element 104 is mounted on the top surface of the base 105.

Abstract: An electronic device includes a semiconductor layer, a primary junction in the semiconductor layer, a lightly doped region surrounding the primary junction and a junction termination structure in the lightly doped region adjacent the primary junction. The junction termination structure has an upper boundary, a side boundary, and a corner between the upper boundary and the side boundary, and the lightly doped region extends in a first direction away from the primary junction and normal to a point on the upper boundary by a first distance that is smaller than a second distance by which the lightly doped region extends in a second direction away from the primary junction and normal to a point on the corner. At least one floating guard ring segment may be provided in the semiconductor layer outside the corner of the junction termination structure. Related methods are also disclosed.

Abstract: A stack package includes a core layer having a first surface and a second surface, and including first circuit wiring lines; a first semiconductor device disposed on the second surface of the core layer; a first resin layer formed on the second surface of the core layer to cover the first semiconductor device; second circuit wiring lines formed on the first resin layer and electrically connected with the first semiconductor device; a second semiconductor device disposed over the first resin layer including the second circuit wiring lines and electrically connected with the second circuit wiring lines; a second resin layer formed on the second circuit wiring lines and the first resin layer to cover the second semiconductor device; and a plurality of via patterns formed to pass through the first resin layer and the core layer and electrically connecting the first circuit wiring lines and the second circuit wiring lines.

Abstract: A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Abstract: The present invention provides an Al alloy film for a display device, to be directly connected to a conductive oxide film on a substrate, the Al alloy film comprising Ge in an amount of 0.05 to 0.5 at %, and comprising Gd and/or La in a total amount of 0.05 to 0.45 at %, a display device using the same, and a sputtering target for the display device. For the Al alloy film of the present invention, even when a barrier metal is not provided, and a conductive oxide film and the Al alloy film are directly connected, the adhesion between the conductive oxide film and the Al alloy film is high, and the contact resistivity is low, and preferably, the dry etching property is also excellent.

Abstract: According to one embodiment, a wafer includes a substrate, a base layer, a foundation layer, an intermediate layer and a functional unit. The substrate has a major surface. The base layer is provided on the major surface and includes a silicon compound. The foundation layer is provided on the base layer and includes GaN. The intermediate layer is provided on the foundation layer and includes a layer including AlN. The functional unit is provided on the intermediate layer and includes a nitride semiconductor. The foundation layer has a first region on a side of the base layer, and a second region on a side of the intermediate layer. A concentration of silicon atoms in the first region is higher than a concentration of silicon atoms in the second region. The foundation layer has a plurality of voids provided in the first region.

Abstract: A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.

Abstract: An FET device characterized as being an asymmetrical tunnel FET (TFET) is disclosed. The TFET includes a gate-stack, a channel region underneath the gate-stack, a first and a second junction adjoining the gate-stack and being capable for electrical continuity with the channel. The first junction and the second junction are of different conductivity types. The TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side.

Abstract: An image sensor including at least one photodiode and at least one transistor formed in and on a silicon substrate, the assembly of the photodiode and of the transistor being surrounded with a heavily-doped insulating wall, wherein the silicon substrate has a crystal orientation (110).

Abstract: A semiconductor device containing a cylindrical shaped capacitor and a method for manufacturing the same is presented. The semiconductor device includes a plurality of storage nodes and a support pattern. The plurality of storage nodes is formed over a semiconductor substrate. The support pattern is fixed to adjacent storage nodes in which the support pattern has a flowable insulation layer buried within the support pattern. The buried flowable insulation layer direct contacts adjacent storage nodes.

Abstract: A display system provides a first semiconductor light source that is electrically connected in a first plane. A second semiconductor light source is electrically connected in a second plane separate from the first plane. A third semiconductor light source is electrically connected in the first plane at least a distance away from the first semiconductor light source equal to the width of the second semiconductor light source. The first plane and the second plane are merged into a combined plane by positioning the electrically connected second semiconductor light source between the electrically connected first semiconductor light source and the electrically connected third semiconductor light source.

Abstract: A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.

Abstract: A hybrid transistor device is provided. In one example case, the device includes a substrate, an oxide layer formed on the substrate, and a wide-bandgap body material formed between a portion of the oxide layer and a gate dielectric layer. The wide-bandgap body material has an energy bandgap higher than that of silicon. The device includes source-drain/emitter material formed on the oxide layer adjacent to the wide-bandgap body material so as to define a hetero-structure interface where the source-drain/emitter material contacts the wide-bandgap body material. The device includes a gate material formed over the gate dielectric layer, a base material formed over a portion of the source-drain/emitter material, and a collector material formed over a portion of the base material. The source-drain/emitter material is shared so as to electrically combine a drain of a first transistor type portion of the device and an emitter of a second transistor type portion.

Abstract: A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.

Abstract: A first conductive gate level feature forms a gate electrode of a first transistor of a first transistor type. A second conductive gate level feature forms a gate electrode of a first transistor of a second transistor type. A third conductive gate level feature forms a gate electrode of a second transistor of the first transistor type. A fourth conductive gate level feature forms a gate electrode of a second transistor of the second transistor type. A first contact connects to the first conductive gate level feature over an inner non-diffusion region. The first and fourth conductive gate level features are electrically connected through the first contact. A second contact connects to the third conductive gate level feature over the inner non-diffusion region and is offset from the first contact. The third and second conductive gate level features are electrically connected through the second contact.

Abstract: A method for reducing dislocations or other defects in a light emitting device, such as light emitting diode (LED), by in-situ introducing nanoparticles into at least one of a defect-controlling layer, an n-type layer, a p-type layer, and a quantum well of the light emitting device. A light emitting device is provided, and nanoparticles are dispensed in-situ in at least one of a defect-controlling layer, an n-type layer, a p-type layer, and a quantum well of the light emitting device.

Abstract: The present invention is a method for producing an SOI substrate including the steps of: preparing a bond wafer and a base wafer which are composed of single crystal silicon wafers; forming an oxide film on a surface of at least one of the bond wafer and the base wafer so that a thickness of a buried oxide film after bonding becomes 3 ?m or more; bonding the bond wafer and the base wafer via the oxide film; performing a low-temperature heat treatment at a temperature of 400° C. or more and 1000° C. or less to the bonded substrate; thinning the bond wafer to be an SOI layer; and increasing bonding strength by performing a high-temperature heat treatment at a temperature exceeding 1000° C. Thus, a method for producing an SOI substrate by which generation of slip dislocations is suppressed and an SOI substrate having a high-quality SOI layer can be obtained, for producing a SOI layer in which the thickness of a buried oxide film is thick as 3 ?m or more by a bonding method, etc. are provided.

Abstract: The invention concerns a module comprising a carrier element, a semiconductor device mounted on said carrier element and a silicon-based insulating layer. The silicon-based insulating layer is arranged on the side of the carrier element opposite to the semiconductor device. The invention further concerns a module comprising a semiconductor device, a mold compound at least partly covering the semiconductor device and a silicon-based passivation layer. The silicon-based passivation layer covers at least partly the periphery of the mold compound.

Abstract: Provided are an image sensor and a package including the same. The image sensor may include an interconnection layer comprising a plurality of interconnections that are vertically stacked, a light penetration layer including color filters and microlenses, a semiconductor layer disposed between the interconnection layer and the light penetration layer and including photoelectrical transformation elements and a light shielding pattern disposed between the light penetration layer and the semiconductor layer. A surface of the semiconductor layer adjacent to the light penetration layer defines a recess region recessed toward the interconnection layer. The light shielding pattern is formed in the recess region and at least one of the photoelectrical transformation elements is formed in the semiconductor layer between the light shielding pattern and the interconnection layer.

Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.