Patents Examined by Whitney T Moore
  • Patent number: 10236382
    Abstract: A semiconductor device includes a buried epitaxially grown substrate and a silicon on insulator (SOI) layer. The device also includes a buried oxide (BOX) layer between the buried epitaxially grown substrate and the SOI layer, an isolation trench having first width (w1), a contact trench having a second width (w2) and a capacitive trench having a third width (w3). Methods are described that allow the formation of the trenches in a normal process flow.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10204821
    Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. Semiconductor devices of the inventive concepts may include a fin region comprising a first fin subregion and a second fin subregion separated and isolated from each other by an isolation insulating layer disposed therebetween, a first gate intersecting the first fin subregion, a second gate intersecting the second fin subregion, and a third gate intersecting the isolation insulating layer.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: HeonJong Shin, Sungmin Kim, Byungseo Kim, Sunhom Steve Paak, Hyunjun Bae
  • Patent number: 10177226
    Abstract: Embodiments are directed to a method of forming a stacked nanosheet and resulting structures having equal thickness work function metal layers. A nanosheet stack is formed on a substrate. The nanosheet stack includes a first sacrificial layer formed on a first nanosheet. A hard mask is formed on the first sacrificial layer and the first sacrificial layer is removed to form a cavity between the hard mask and the first nanosheet. A work function layer is formed to fill the cavity between the hard mask and the first nanosheet.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: January 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Nicolas J. Loubet
  • Patent number: 10170581
    Abstract: A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Veeraraghavan S. Basker, Sivananda K. Kanakasabapathy
  • Patent number: 10164191
    Abstract: The present invention relates to a methoxyaryl surface modifier. In addition the present invention also relates to organic electronic devices comprising such methoxyaryl surface modifier.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: December 25, 2018
    Assignees: Merck Patent GmbH, InnovationLab GmbH, Technische Universitaet Braunschweig, Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E.V.
    Inventors: Malte Jesper, Manuel Hamburger, Janusz Schinke, Milan Alt, Klaus Muellen
  • Patent number: 10162237
    Abstract: A display device includes a first substrate including a display area and a peripheral area disposed in a periphery of the display area. A gate line is disposed in the display area. A data line is insulated from the gate line and intersects the gate line. The data line includes a first portion and a second portion. The first portion is disposed in the display area, and the second portion is connected to the first portion and is disposed in the peripheral area. A thin-film transistor (TFT) is disposed in the display area of the first substrate and is connected to the gate and data lines. A first insulating pattern is disposed on the TFT. A second insulating pattern is disposed in the peripheral area and covers a part of the second portion of the data line. The second insulating pattern includes a same material as the first insulating pattern.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jee Hoon Han, Soo Chul Kim, Jae Yong Shin, Jae Hyoung Youn
  • Patent number: 10163721
    Abstract: A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Donald F. Canaperi, Thamarai S. Devarajan, Sivananda K. Kanakasabapathy, Fee Li Lie, Peng Xu
  • Patent number: 10158008
    Abstract: A change in electrical characteristics of a semiconductor device including an oxide semiconductor is prevented, and the reliability of the semiconductor device is improved. An oxide semiconductor is formed over a substrate; an insulator is formed over the oxide semiconductor; a metal oxide is formed over the insulator; a conductor is formed over the metal oxide; a portion of the oxide semiconductor is exposed by removing the conductor, the metal oxide, and the insulator over the oxide semiconductor; plasma treatment is performed on a surface of the exposed portion of the oxide semiconductor; and a nitride insulator is formed over the exposed portion of the oxide semiconductor and over the conductor. The plasma treatment is performed in a mixed atmosphere of an argon gas and a nitrogen gas.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: December 18, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Masami Jintyou, Yukinori Shima, Yasuharu Hosaka, Yasutaka Nakazawa, Takashi Hamochi, Takahiro Sato, Shunpei Yamazaki
  • Patent number: 10158009
    Abstract: A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: December 18, 2018
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler
  • Patent number: 10141291
    Abstract: The present disclosure relates to a semiconductor device and method of manufacturing the same. The method for manufacturing a semiconductor device includes: attaching a carrier wafer to a front side of a top die wafer; thinning a back side of the top die wafer, the back side of the top die wafer being opposite to the front side the top die wafer; singulating the carrier wafer and the top die wafer whereby singulated dies attached to singulated carrier dies are formed; and bonding back side of each of the singulated dies to a front side of a bottom die wafer.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Liang Shao, Chih-Hang Tung, Chen-Hua Yu
  • Patent number: 10134705
    Abstract: As one embodiment, a method of manufacturing a semiconductor device includes the following steps. That is, the method of manufacturing a semiconductor device includes a first step of applying ultrasonic waves to a ball portion of a first wire in contact with a first electrode of the semiconductor chip while pressing the ball portion with a first load. In addition, the method of manufacturing a semiconductor device includes a step of, after the first step, applying the ultrasonic waves to the ball portion while pressing the ball portion with a second load larger than the first load, thereby bonding the ball portion and the first electrode.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yuko Matsubara
  • Patent number: 10134771
    Abstract: An array substrate, a method of producing the array substrate, and a display panel incorporating the array substrate are disclosed. The array substrate includes a substrate, a gate line, a data line, and a spacer. The gate line and the data line are arranged over the substrate. The spacer is arranged over the gate line and the data line. The gate line and/or the data line is provided with a via hole at a position corresponding to a spacer. In this manner, a problem of a display panel having gaps of different sizes after assembly because of non-uniform thicknesses of the gate line and/or the data line can be avoided, which, in turn, prevents inhomogeneous color in the display.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: November 20, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING, BOE DISPLAY TECHNOLOGY GROUP CO., LTD.
    Inventors: Yusheng Xi, Haichen Hu, Ming Tian
  • Patent number: 10134689
    Abstract: A wafer level package device and method are disclosed that include a warpage compensation metal adhered to a backside of a semiconductor wafer for minimizing warpage of the semiconductor wafer, where multiple metal features have been formed on the device side of the semiconductor substrate. The warpage compensation metal may include a copper film.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: November 20, 2018
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Vivek S. Sridharan, Amit S. Kelkar, Sriram Muthukumar
  • Patent number: 10121984
    Abstract: A light-emitting element which uses a plurality of kinds of light-emitting dopants emitting light in a balanced manner and has high emission efficiency is provided. Further, a light-emitting device, a display device, an electronic device, and a lighting device each having reduced power consumption by using the above light-emitting element are provided. A light-emitting element which includes a plurality of light-emitting layers including different phosphorescent materials is provided. In the light-emitting element, the light-emitting layer which includes a light-emitting material emitting light with a long wavelength includes two kinds of carrier-transport compounds having properties of transporting carriers with different polarities. Further, in the light-emitting element, the triplet excitation energy of a host material included in the light-emitting layer emitting light with a short wavelength is higher than the triplet excitation energy of at least one of the carrier-transport compounds.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: November 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Takahiro Ishisone
  • Patent number: 10121846
    Abstract: The present disclosure provides resistor structures in sophisticated integrated circuits on the basis of an SOI architecture, wherein a very thin semiconductor layer, typically used for forming fully depleted SOI transistors, may be used as a resistor body. In this manner, significantly higher sheet resistance values may be achieved, thereby providing the potential for implementing high ohmic resistors into sophisticated integrated circuits.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alban Zaka, Ignasi Cortes Mayol, Tom Herrmann, El Mehdi Bazizi, John Morgan
  • Patent number: 10121927
    Abstract: A provided semiconductor device includes a Ge photodiode having proper diode characteristics. A groove is provided on a germanium growth protective film, a p-type silicon layer, and a first insulating film from the top surface of the germanium growth protective film without reaching the major surface of a semiconductor substrate. An i-type germanium layer and an n-type germanium layer are embedded in the groove with a seed layer interposed between the layers and the groove, the seed layer being made of amorphous silicon, polysilicon, or silicon germanium. The i-type germanium layer and the n-type germanium layer do not protrude from the top surface of the germanium growth protective film, thereby forming a flat second insulating film having a substantially even thickness on the n-type germanium layer and the germanium growth protective film.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: November 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Tomoo Nakayama
  • Patent number: 10115811
    Abstract: A vertical channel semiconductor device including: a semiconductor body including a substrate having a first conductivity type and a front layer having a second conductivity type; a first portion of trench and a second portion of trench; and, within the first and second portions of trench, a corresponding conductive region and a corresponding insulating layer. The first and second portions of trench delimit laterally a first semiconductor region and a second semiconductor region, the first semiconductor region having a maximum width greater than the maximum width of the second semiconductor region. The device further includes an emitter region having the first conductivity type, which extends in the front layer and includes: a full portion, which extends in the second semiconductor region; and an annular portion, which extends in the first semiconductor region. The annular portion laterally surrounds a top region having the second conductivity type.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 30, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fernando Giovanni Menta, Salvatore Pisano
  • Patent number: 10109599
    Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Cathryn J. Christiansen, Anthony K. Stamper, Tom C. Lee, Ian Mccallum-Cook
  • Patent number: 10109787
    Abstract: A vertical Hall element and method of fabricating are disclosed. The method includes forming a buried region having a first conductivity type in a substrate having a second conductivity type and implanting a dopant of the first conductivity type into a well region between the top surface of the substrate and the buried region. The buried region has a doping concentration increasing with an increasing depth from a top surface of the substrate and the well region has a doping concentration decreasing from the top surface of the substrate to the buried region. The method includes forming first through fifth contacts on the well region. First and second contacts define a conductive path and second and third contacts define another conductive path through the well region. The fourth contact is formed between first and second contacts and the fifth contact is formed between second and third contacts.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: October 23, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Keith Ryan Green, Iouri Mirgorodski
  • Patent number: 10109546
    Abstract: In order to carry out the encapsulation of electronic components, the invention proposes to cover the electronic components (7) with a heat-polymerisable material corresponding to a composition comprising a diimide constituent and a diamine constituent, in which the diimide constituent has been predissolved in the diamine constituent, and to heat the assembly obtained under conditions suitable for carrying out the curing of the material by an addition polymerization reaction between said diimide constituent and the diamine constituent. The invention finds an application in particular in the field of electronic power modules.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: October 23, 2018
    Assignee: Valeo Equipements Electriques Moteur
    Inventors: Arnaud Soisson, Philippe Banet, Linda Chikh, Odile Fichet