Abstract: method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method includes use of a polishing pad with a slurry solution in which copper and a material, such as tungsten, of the barrier layer are removed at substantially the same rate. The slurry is formulated so as to oxidize copper and a material of the barrier layer at substantially the same rates. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.

Abstract: A process including the steps of: carrying out a directional etching in a semiconductor material body to form trenches having a first width; carrying out an isotropic etching of the semiconductor material body under the trenches to form cavities having a width larger than the trenches; covering the walls of the cavities with dielectric material; depositing non-conducting material different from thermal oxide to fill the cavities at least partially, so as to form a single-crystal island separated from the rest of the semiconductor material body. The isotropic etching permits the formation of at least two adjacent cavities separated by a support region of semiconductor material, which is oxidized together with the walls of the cavities to provide a support to the island prior to filling with non-conducting material.

Abstract: A method of forming a notch silicon-containing gate structure is disclosed. This method is particularly useful in forming a T-shaped silicon-containing gate structure. A silicon-containing gate layer is etched to a first desired depth using a plasma generated from a first source gas. During the etch, etch byproducts deposit on upper sidewalls of the silicon-containing gate layer which are exposed during etching, forming a first passivation layer which protects the upper silicon-containing gate layer sidewalls from etching during subsequent processing steps. A relatively high substrate bias power is used during this first etch step to ensure that the passivation layer adheres properly to the upper silicon-containing gate sidewalls.

Abstract: A method and apparatus for planarizing a microelectronic substrate. In one embodiment, the microelectronic substrate is engaged with a planarizing medium that includes a planarizing pad and a planarizing liquid. The planarizing liquid has a selected pH and abrasive elements in the planarizing pad have an isoelectric point that is at or below the pH of the planarizing liquid. For example, the abrasive elements can include coated or conglomerate elements formed from two materials, each having a different isoelectric point. Alternatively, different abrasive elements in the planarizing pad can have different isoelectric points. Accordingly, the abrasive elements can have a reduced affinity for components of the planaring liquid, such as corrosion-inhibiting agents. In another embodiment, high-frequency radiation, such as ultraviolet radiation, is directed toward the planarizing medium to control an amount of the corrosion-inhibiting agent adsorbed to the abrasive elements.

Abstract: A method of manufacturing a planar or integrated optical circuit in which a core layer (20) is formed on a substrate (10) and patterned to define optical features (such as waveguides) using a mask having a first portion (30) defining the desired core patterns (20a) and a second portion (35) corresponding to one or more alignment marks (20b). After etching the core layer, only the first portion (30) of the mask is removed, the second portion (35) of the mask being left to provide alignment marks (20b) which are highly visible through the subsequently-deposited overclad layer (40). The alignment marks (20b) are very accurately positioned with respect to the core patterns (20a), thus enabling further optical devices to be overlaid on the existing structure with accurate alignment to the underlying core patterns. The mask material (35) left on the alignment marks (20b) may be partially oxidized before the overclad is deposited.

Abstract: A microelectromechanical (MEMS) device and a method of fabricating a MEMS device are provided. The method of fabricating the MEMS device includes the steps of: etching a die release trench in a primary handle layer of a wafer having the handle layer, an etch-stop layer disposed on the primary handle layer, and a device layer disposed on the etch-stop layer; patterning a release trench in the device layer that is aligned with the release trench in the primary handle layer; temporarily attaching an additional handle layer to the primary handle layer; etching the device layer to define a structure in the device layer; removing the etch-stop layer; and removing the additional handle layer to release the die.

Abstract: The present invention provides a chemical mechanical polishing composition for planarizing copper and a method for planarizing, or initiating the planarization of, copper using the composition. The chemical mechanical polishing composition includes an oxidizing agent and a copper (II) compound. The composition optionally includes one or more of the following compound types: a complexing agent; a corrosion inhibitor; an acid; and, an abrasive. In one embodiment, the oxidizing agent is hydrogen peroxide, ferric nitrate or an iodate. In another embodiment, the copper (II) compound is CuSO4. The chemical mechanical polishing method involves the step of polishing a copper layer using a composition that includes an oxidizing agent and a copper (II) compound. The composition is formed in a variety of ways. In one embodiment, it is formed by adding the copper (II) compound to a solution containing the oxidizing agent, and any included optional compound types, in deionized water.

Abstract: A method of using lubricating boundary layers for finishing semiconductor wafers is described. The lubricating boundary layer thickness is controlled to improve finishing and reduce unwanted surface defects. Differential lubricating boundary layer methods are described to differentially finish semiconductor wafers. Planarization and localized finishing can be improved using differential lubricating boundary layer methods of finishing.

Abstract: A method of removing Chemical Mechanical Polishing (CMP) residue from a semiconductor substrate is disclosed. The semiconductor substrate with the CMP residue on a surface is placed within a pressure chamber. The pressure chamber is then pressurized. Supercritical carbon dioxide and a solvent are introduced into the pressure chamber. The supercritical carbon dioxide and the chemical are maintained in contact with the semiconductor substrate until the CMP residue is removed from the semiconductor substrate. The pressure chamber is then flushed and vented.

Abstract: The present invention includes methods and apparatus as described in the claims. Briefly, semiconductor diodes having a low forward conduction voltage drop, a low reverse leakage current, a high voltage capability and avalanche energy capability, suitable for use in integrated circuits as well as for discrete devices are disclosed. The semiconductor diodes are diode configured vertical cylindrical metal oxide semiconductor field effect devices having one diode terminal as the common connection between the gates and drains of the vertical cylindrical metal oxide semiconductor field effect devices, and one diode terminal as the common connection with the sources of the vertical cylindrical metal oxide semiconductor field effect devices. The method of manufacturing the vertical cylindrical metal oxide semiconductor field effect devices is disclosed. Various device terminations can be employed to complete the diode devices. Various embodiments are disclosed.

Abstract: A method and apparatus for planarizing a microelectronic substrate. In one embodiment, the method can include planarizing the microelectronic substrate with a fixed abrasive polishing pad while maintaining the pH of a planarizing liquid adjacent the polishing pad at an approximately constant level by buffering the planarizing liquid. The planarizing liquid can include ammonium hydroxide and ammonium acetate, ammonium citrate, or potassium hydrogen phthalate. In another embodiment, the planarizing liquid can have an initially high pH that has a reduced tendency to decrease during planarization.

Abstract: A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the substrate. In the etching process, the substrate is positioned in a processing chamber, a processing gas comprising a fluorocarbon, which advantageously is a hydrogen free fluorocarbon, is introduced into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch the silicon based material of the substrate. The processing gas may further comprise an inert gas, such as argon.

Abstract: A method of forming an organosilicate layer is disclosed. The organosilicate layer is formed by applying an electric field to a gas mixture comprising an organosilane compound and an oxygen-containing gas. The organosilicate layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the organosilicate layer is used as an intermetal dielectric layer. In another integrated circuit fabrication process, the organosilicate layer is incorporated into a damascene structure.

Abstract: A monolithic inkjet printhead formed using integrated circuit techniques is described. A silicon substrate has formed on its top surface a thin polysilicon layer in the area in which a trench is to be later formed in the substrate. The edges of the polysilicon layer align with the intended placement of ink feed holes leading into ink ejection chambers. Thin film layers, including a resistive layer, are formed on the top surface of the silicon substrate and over the polysilicon layer. An orifice layer is formed on the top surface of the thin film layers to define the nozzles and ink ejection chambers. A trench mask is formed on the bottom surface of the substrate. A trench is etched (using, for example, TMAH) through the exposed bottom surface of the substrate and to the polysilicon layer. The etching of the polysilicon layer exposes fast etch planes of the silicon. The TMAH then rapidly etches the silicon substrate along the etch planes, thus aligning the edges of the trench with the polysilicon.

Abstract: An apparatus and method for polishing the surface of a semiconductor wafer is provided in which the polishing pad has on its surface a multiplicity of nanoasperities which are particles having an imputed radius (of curvature) of about 0.5 to about 0.1 microns and sufficient resiliency to permanently deform by less than 10% which contact the wafer surface in combination with a reactive liquid solution which may be recirculated, analyzed, adjusted, and from which soluble reaction products may be removed.

Abstract: A two-step etch method for etching a masked layer or layers that include fast and slow etching regions is described. Fast and slow etching regions may arise in a variety of devices, such as microelectrical mechanical system (“MEMS”) applications and mixed signal (i.e. analog and digital) integrated circuits, as well as other integrated circuits and devices. In one embodiment, a first etchant is used to etch through the layer in the fastest etching region, and then a second etchant is used to complete etching through the layer in the slowest etching region.

Abstract: An exemplary method is described which forms narrow trench lines having a critical dimension which is smaller than the critical dimension possible using conventional lithographic techniques. This method can include providing a hard mask over a layer of material in which a trench line is to be formed; etching the hard mask with a first critical dimension at the top of the hard mask and a second critical dimension at the bottom of the hard mask; and etching a trench line using the hard mask to transfer the second critical dimension to the trench line.

Abstract: A process for the double-side polishing of semiconductor wafers between two polishing plates which rotate in opposite directions and are covered with polishing cloth, so that at least 2 &mgr;m of semiconductor material is removed. The semiconductor wafers lay in plastic-lined cutouts in a set of a plurality of planar carriers which are made from steel and the mean thickness of which is 2 to 20 &mgr;m smaller than the mean thickness of the fully polished semiconductor wafers. The set comprises only those carriers whose difference in thickness is at most 5 &mgr;m, and each carrier belonging to the set has at least one unambiguous identification feature which assigns it to the set. An item of information contained in the identification feature is used in order for the plastic linings to be exchanged at fixed intervals and to ensure that the semiconductor wafers remain in the same order after the polishing as before the polishing. There is also a carrier which is suitable for carrying out the process.

Abstract: An exemplary method is described which forms a contact hole having a critical dimension which is smaller than the critical dimension possible using conventional lithographic techniques. This method can include providing a hard mask over a layer of material in which a contact hole is to be formed; etching the hard mask with a first critical dimension at the top of the hard mask and a second critical dimension at the bottom of the hard mask; and etching a contact hole using the hard mask to transfer the second critical dimension to the contact hole.

Abstract: A novel method of Cu seed layer deposition for ULSI metalization is disclosed. The method of Cu seed layer deposition for ULSI metalization comprises forming a diffusion barrier on a substrate, forming a poly silicon layer, amorphous silicon layer or TaSix layer on said diffusion barrier, replacing said poly silicon layer with copper to form a copper seed layer, and electroplating a thick copper film on said copper seed layer. In this invention, a chemical replacing solution comprising a replacing reactant and at least one etchant is used to replace the poly silicon layer with copper and to reduce the quantity of byproducts of the reaction.