Abstract: There is disclosed a modular lamination approach for processing organic photosensitive devices that allows the individual processing of device components, that once processed are brought together in a final step to make electrical contact. The disclosed method of preparing a laminated photosensitive device having at least one donor-acceptor heterojunction comprises: preparing a top electrode by depositing a functional material on a flexible substrate, such as an elastomer; optionally processing the functional material to obtain desired properties prior to lamination; preparing a bottom portion by depositing a second functional material over a substrate; optionally processing the second functional material to obtain desired properties prior to lamination; and coupling the top electrode to said bottom portion to form a laminated photosensitive device.

Abstract: A semiconductor device includes a carrier substrate having at least one conductor track, at least one converter element structured at least partly from a further semiconductor substrate, and conductive structures formed on a respective converter element. The at least one converter element is electrically linked to the at least one conductor track via at least one at least partly conductive supporting element arranged between a contact side of the carrier substrate and an inner side of the converter element. The inner side is oriented toward the carrier substrate. The at least one converter element is arranged on the contact side of the carrier substrate such that the inner side of the converter element is kept spaced apart from the contact side of the carrier substrate. The at least one converter element and the conductive structures formed thereon are completely embedded into at least one insulating material.

Abstract: Disclosed herein is a micro electro mechanical systems (MEMS) device including: a mass body; a first fixed part provided at an outer side of the mass body; and a first flexible part having one end connected to a distal end of the mass body and the other end connected to the first fixed part, wherein the mass body is rotatably connected to the first flexible part.

Abstract: Prepared in advance is a substrate formed of metallic material where slits are formed between mounting regions. Oxide films are generated all over the substrate including end faces of the substrate. Exposed are only lateral faces corresponding to the cross sections cut when tie bars are cut. This structure and the fabrication method minimize the area of cutting faces in the metallic material.

Abstract: A semiconductor device includes a semiconductor layer and a Schottky electrode, a Schottky junction being formed between the semiconductor layer and the Schottky electrode. The Schottky electrode includes a metal part containing a metal, a Schottky junction being formed between the semiconductor layer and the metal part; and a nitride part around the metal part, the nitride part containing a nitride of the metal, and a Schottky junction being formed between the semiconductor layer and the nitride part.

Abstract: An imaging system may include an image sensor having an array of image pixels formed in a substrate. Each image pixel may include a photodiode directly coupled to an anti-blooming diode. The anti-blooming diode may be connected to a positive voltage supply line and may be configured to drain excess charge from the photodiode when the photodiode is saturated. The anti-blooming drain may be formed from an n-type diffusion region partially surrounded by a p-type doped layer. The p-type doped layer may be interposed between and in contact with the n-type diffusion region of the anti-blooming diode and an n-type doped region of the photodiode. The anti-blooming diode may begin to drain excess charge from the photodiode in response to the photodiode reaching a threshold potential during integration. If desired, multiple pixels may share a common anti-blooming diode.

Abstract: Disclosed are semiconductor-on-insulator (SOI) structures comprising an SOI device (e.g., an SOI metal oxide semiconductor field effect transistor (MOSFET)) with local heat dissipater(s). Each heat dissipater comprises an opening, which is adjacent an active region of the SOI device, which extends through the insulator layer on which the SOI device sits to the semiconductor substrate below, and which is at least partially filled with a fill material. This fill material is a thermal conductor so as to dissipate heat generated by the SOI device and is also an electrical isolator so as to minimize current leakage. In the case of MOSFET, the local heat dissipater(s) can be aligned below the source/drain extension(s) or the source/drain(s). Alternatively, the local heat dissipater(s) can be aligned below the channel or parallel and adjacent to opposing sides of the channel. Also disclosed herein are methods of forming these SOI structures.

Abstract: Mechanical resonating structures, as well as related devices and methods of manufacture. The mechanical resonating structures can be microphones, each including a diaphragm and a piezoelectric stack. The diaphragm can have one or more openings formed therethrough to enable the determination of an acoustic pressure being applied to the diaphragm through signals emitted by the piezoelectric stack.

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

Abstract: An imaging system may include an image sensor package with an image sensor wafer mounted on a carrier wafer, which may be a silicon substrate. A capacitor may be formed in the carrier wafer. Trenches may be etched in a serpentine pattern in the silicon substrate. Conductive plates of the capacitor may be formed at least partially in the trenches. An insulator material may be formed between the capacitor and the silicon substrate. A dielectric layer may be formed between the conductive plates of the capacitor. The image sensor package may be mounted on a printed circuit board via a ball grid array. Conductive vias may electrically couple the capacitor and the image sensor wafer to the printed circuit board.

Abstract: A device includes a support structure, a sound port disposed in the support structure, and a MEMS structure including a membrane acoustically coupled to the sound port. The membrane separates a first space contacting a first side of the membrane from a second space contacting an opposite second side of the membrane. The device further includes an adjustable ventilation path disposed in the support structure and extending from the sound port to the second space.

Abstract: Optical absorbers, solar cells comprising the absorbers, and methods for making the absorbers are disclosed. The optical absorber comprises a semiconductor layer having a bandgap of between about 1.0 eV and about 1.6 eV disposed on a substrate, wherein the semiconductor comprises two or more earth abundant elements. The bandgap of the optical absorber is graded through the thickness of the layer by partial substitution of at least one grading element from the same group in the periodic table as the at least one of the two or more earth abundant elements.

Abstract: There is provided a wiring board for mounting a light emitting element thereon. The wiring board includes: an insulating layer; a wiring pattern on the insulating layer; a reflecting layer on the insulating layer to cover the wiring pattern, wherein the light emitting element is to be mounted on a surface of the reflecting layer; and a silica film on the surface of the reflecting layer.

Abstract: A high-voltage MEMS system compatible with low-voltage semiconductor process technology is disclosed. The system comprises a MEMS device coupled to a high-voltage bias generator employing an extended-voltage isolation residing in a semiconductor technology substrate. The system avoids the use of high-voltage transistors so that special high-voltage processing steps are not required of the semiconductor technology, thereby reducing process cost and complexity. MEMS testing capability is addressed with a self-test circuit allowing modulation of the bias voltage and current so that a need for external high-voltage connections and associated electro-static discharge protection circuitry are also avoided.

Abstract: Disclosed is a light emitting device. A light emitting device comprises a plurality of N-type semiconductor layers including a first N-type semiconductor layer and a second N-type semiconductor layer on the first N-type semiconductor layer, an active layer on the second N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein the first N-type semiconductor layer comprises a Si doped Nitride layer and the second N-type semiconductor layer comprises a Si doped Nitride layer, and wherein the first and second N-type semiconductor layers have a Si impurity concentration different from each other.

Abstract: According to one embodiment, a strain sensor includes a substrate, a lid, a frame, and a sensing unit. The substrate has a first surface. The lid is provided on the first surface. The frame is provided between the substrate and the lid. The frame is nonconductive and includes a magnetic body. The sensing unit is provided inside the frame between the substrate and the lid, and includes a magnetoresistance effect element.

Abstract: An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.

Abstract: A non-planar semiconductor with enhanced strain includes a substrate and at least one semiconducting fin formed on a surface of the substrate. A gate stack is formed on a portion of the at least one semiconducting fin. A stress liner is formed over at least each of a plurality of sidewalls of the at least one semiconducting fin and the gate stack. The stress liner imparts stress to at least a source region, a drain region, and a channel region of the at least one semiconducting fin. The channel region is located in at least one semiconducting fin beneath the gate stack.

Abstract: A pixel array includes a plurality of photodiodes disposed in a semiconductor layer and arranged in the pixel array. A color filter layer is disposed proximate to the semiconductor layer. Light is to be directed to at least a first one of the plurality of photodiodes through the color filter layer. An optical shield layer is disposed proximate to the color filter layer. The color filter layer is disposed between the optical shield layer and the semiconductor layer. The optical shield layer shields at least a second one of the plurality of photodiodes from the light.

Abstract: An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. Second doped base regions discretely located in a fourth region of a first P-type well region are P-type doped and connected to the external trigger-voltage adjustment circuit. A first N-region is located in the fourth region, surrounding the second doped base regions, and connected to the I/O interface terminal. A second N-region is located in the fourth region, surrounding the first N-region and the second doped base regions, and connected to the ground terminal.