Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. For example, a method includes applying a protection tape to a wafer front side, the wafer having a dicing tape attached to the wafer backside. The dicing tape is removed from the wafer backside to expose a die attach film disposed between the wafer backside and the dicing tape. Alternatively, if no die attach film is initially disposed between the wafer backside and the dicing tape, a die attach film is applied to the wafer backside at this operation. A water soluble mask is applied to the wafer backside. Laser scribing is performed on the wafer backside to cut through the mask, the die attach film and the wafer, including all layers included within the front side and backside of the wafer. A plasma etch is performed to treat or clean surfaces of the wafer exposed by the laser scribing. A wafer backside cleaning is performed and a second dicing tape is applied to the wafer backside.

Abstract: An organic molecular memory for controlling a current flowing through a memory cell and achieving stable operation and high degree of reliability is provided. The organic molecular memory includes a first electrode, a second electrode made of a material different from the first electrode, and an organic molecule layer provided between the first electrode and the second electrode, wherein one end of a resistance change-type molecular chain constituting the organic molecule layer is chemically bonded with the first electrode, and an air gap exists between the other end of the resistance change-type molecular chain and the second electrode.

Abstract: An ESD protection structure and a semiconductor device having an ESD protection structure with the ESD protection structure including a patterned conductive ESD protection layer. The ESD protection layer is patterned to have a first portion of a substantially closed ring shape having an outer contour line and an inner contour line parallel with each other. The outer and the inner contour lines are waved lines. The first portion further has a midline between and parallel with the outer and the inner contour lines. The midline is a waved line having a substantially constant curvature at each point of the midline. Therefore the ESD protection layer has a substantially uniform curvature and an increased perimeter which advantageously improve the breakdown voltage and the current handling capacity of the ESD protection structure.

Abstract: A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

Abstract: A multi-gate semiconductor device with inter-gate conductive regions being connected to balance resistors is provided. The multi-gate semiconductor device comprises a substrate, a multilayer structure formed upon the substrate, a first ohmic electrode, a second ohmic electrode, a plural of gate electrodes, at least one conductive region, and at least one resistive component. When put into practice, the multi-gate semiconductor device is advantageous in reducing the voltage drop along the conductive region with a minimal change in device layout, improving the OFF-state linearity while retaining a low insertion loss, and minimizing the area occupied by the resistor and hence the total chip size.

Abstract: The invention relates to measurement and control of mechanical values, in particular, to control of stress conditions of various structures and manufacturing sensors of resistant strain gauge type for measuring various mechanical values. It can be used in manufacturing sensors of deformation, force, pressure, movement, vibration etc. to increase accuracy in resistant strain gauge measuring at sensitivity preservation. The resistant strain gauge for deformation and pressure measuring represents a dielectric substrate with spread strain-sensing layer in state of polycrystalline film, which contains samarium sulfide, and metal contact pads. Pads are placed on the same side of a film and output signals are soldered to them. Strain-sensing layer comprises holes which connect the pads. According to the first option, strain-sensing layer has the following composition Sm1?xLnxS, where Ln is one from the elements: La, Ce, Pr, Nd, Gd, Tb, Dy, Ho, Er, Tm, Lu, Y, at 0<x<0.3.

Abstract: A method for forming magnetic conductors includes forming a metal structure on a substrate. Plating surfaces are prepared on the metal structure for electroless plating by at least one of: masking surfaces of the metal structure to prevent electroless plating on masked surfaces and/or activating a surface of the metal structure. Magnetic material is electrolessly plated directly on the plating surfaces to form a metal and magnetic material structure.

Abstract: According to one embodiment, a light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a first insulating layer, a p-side interconnect layer, an n-side interconnect layer and a second insulating layer. The semiconductor layer includes a first surface, a second surface opposite to the first surface, and a light emitting layer. The p-side electrode is provided on the second surface in a region including the light emitting layer. The n-side electrode is provided on the second surface in a region not including the light emitting layer. The p-side interconnect layer includes a p-side external terminal exposed from the second insulating layer at a third surface having a plane orientation different from a plane orientation of the first surface and a plane orientation of the second surface. The n-side interconnect layer includes an n-side external terminal exposed from the second insulating layer at the third surface.

Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.

Abstract: A MEMS apparatus includes a pillar, a supporter, and a solder. The pillar has a first side and a second side opposite to the first side. The supporter supports the pillar. The supporter is adjacent to the pillar, but the supporter is not connected to the pillar. The supporter has a third side and a fourth side opposite to the third side. The supporter includes a plurality of first confined layers and a plurality of second confined layers. These first confined layers and these second confined layers are overlapped with each other. The second side and the third side are adjacent to each other. The solder is located between the second side and the third side. The solder is also located at the first side and the fourth side. The solder is utilized to combine the pillar and the supporter. The solder also isolates the pillar and the supporter.

Abstract: A mask read only memory containing diodes and method of manufacturing the same. The mask read only memory is a high-density three dimensional array formed by stacking a plurality of diode layers and the logic “0” or “1” is defined by whether there is a dielectric layer on the diode.

Abstract: A semiconductor device includes a gate electrode which is formed on a substrate, and contains Al and Zr, a gate insulating film which is formed to cover at least the upper surface of the gate electrode, and contains Al and Zr, and an insulator layer formed on the substrate to surround the gate electrode.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In an embodiment, a method of manufacturing a semiconductor device includes forming a first conductive structure over a workpiece in a first metallization layer, the first conductive structure including a first portion having a first width and a second portion having a second width. The second width is different than the first width. The method includes forming a second conductive structure in a second metallization layer proximate the first metallization layer, and coupling a portion of the second conductive structure to the first portion of the first conductive structure.

Abstract: An image pickup apparatus includes a semiconductor chip including a light receiving section, a frame-like spacer arranged on the semiconductor chip to surround the light receiving section, a transparent flat plate section arranged on the semiconductor chip via the spacer and having a plan view dimension larger than a plan view dimension of the spacer and smaller than a plan view dimension of the semiconductor chip, and a reinforcing member for filling a gap between the semiconductor chip and the transparent flat plate section on the outer side of the spacer and having a plan view dimension larger than the plan view dimension of the transparent flat plate section and smaller than the plan view dimension of the semiconductor chip.

Abstract: A pixel cell includes a storage transistor including a deep implant storage region having a first polarity is implanted in a semiconductor substrate to store image charge accumulated by a photodiode. A transfer transistor is coupled between the photodiode and an input of the storage transistor to selectively transfer the image charge from the photodiode to the storage transistor. An output transistor is coupled to an output of the storage transistor to selectively transfer the image charge from the storage transistor to a readout node. A first shallow implant region having the first polarity is implanted in the semiconductor substrate under a first spacer region between a transfer gate of the transfer transistor and a storage gate of the storage transistor. A second shallow implant region having the first polarity is implanted in the semiconductor substrate under a second spacer region between the storage gate and the output gate.

Abstract: In some embodiments, a circuit element includes a first FET and a first storage capacitor. The first FET includes a gate stack, a first source or drain region, a second source or drain region and a body structure. The gate stack is configured over the body structure. The first source or drain region and the second source or drain region are configured on opposite sides of the gate stack. The first storage capacitor includes an anode and a cathode. The first source or drain region is coupled to the anode of the first storage capacitor non-selectively, and does not have stressor material with a lattice constant different from that of a channel region in the body structure. The second source or drain structure is coupled to the anode of the first storage capacitor selectively, and has the stressor material.

Abstract: A method and apparatus (1) for machining a semiconductor or ceramic workpiece (32) causes a portion of the workpiece to undergo high pressure phase transformation to form a high pressure phase transformation portion which has altered optical properties from the remainder of the workpiece. A laser is irradiated on the high pressure transformation portion to heat the high pressure transformation portion and cause it to soften and then the workpiece is plastically deformed, at smaller loads and forces, along the softened portion in order to accomplish the machining of the workpiece with a machining tool (21).

Abstract: A structure for growth of a nitride semiconductor layer which is disclosed in this application includes: a sapphire substrate of which growing plane is an m-plane; and a plurality of ridge-shaped nitride semiconductor layers provided on the growing plane of the sapphire substrate, wherein a bottom surface of a recessed portion provided between respective ones of the plurality of ridge-shaped nitride semiconductor layers is the m-plane of the sapphire substrate, the growing plane of the plurality of ridge-shaped nitride semiconductor layers is an m-plane, and an absolute value of an angle between an extending direction of the plurality of ridge-shaped nitride semiconductor layers and a c-axis of the sapphire substrate is not less than 0° and not more than 35°.

Abstract: A memory device includes a MISFET on a semiconductor substrate of a first conductivity type, and a MIS capacitor on a first well of a second conductivity type. The MISFET includes a gate insulating film on the semiconductor substrate, a gate electrode, and a source/drain located at both sides of the gate electrode. The MIS capacitor includes a capacitor insulating film on the first well serving as a first electrode, a second electrode, and a first impurity layer of the first conductivity type. The gate electrode and the second electrode are electrically connected together, and form a floating gate. The gate insulating film and the capacitor insulating film are made of a same material, and have a same thickness. The gate electrode and the second electrode are made of a same conductive film. A second impurity layer is formed astride a border between the semiconductor substrate and the first well.

Abstract: A method for manufacturing a device having a concavo-convex structure includes forming an organic resist film on an n-type semiconductor layer in which a fine concavo-convex structure is to be formed; forming a silicon-containing resist film on the organic resist film; patterning the silicon-containing resist film by nanoimprint; oxidizing the silicon-containing resist film with oxygen-containing plasma to form a silicon oxide film; dry-etching the organic resist film by using the silicon oxide film as an etching mask; dry-etching the n-type semiconductor layer by using the silicon oxide film and the organic resist film as an etching masks; and removing the silicon oxide film and the organic resist film.