Abstract: The present invention is directed toward apparatus and methods of testing and assembling bumped die and bumped devices using an anisotropically conductive layer. In one embodiment, a semiconductor device comprises a bumped device having a plurality of conductive bumps formed thereon, a substrate having a plurality of contact pads distributed thereon and approximately aligned with the plurality of conductive bumps, and an anisotropically conductive layer disposed between and mechanically coupled to the bumped device and to the substrate. The anisotropically conductive layer electrically couples each of the conductive bumps with a corresponding one of the contact pads.

Abstract: A method of forming an underfilled semiconductor package comprises the steps of: providing a substrate (300) with raised terminal portions (305), disposing underfill compound (5) with filler (27) on the substrate (300), placing a bumped semiconductor die (40) on the substrate (300) with bumps (45) abutting upper surfaces (310) of the raised terminal portions (305), and reflowing the assembly. During the reflow process, the raised terminal portions (305) and the bumps (45) melt and displace the filler (27) in the underfill compound (5) away from between the bumps (45) and the raised terminal portions (305). This prevents the filler (27) from forming a barrier. The molten solder forms interconnects between the pads (46) and the raised terminal portions (305).

Abstract: A method is disclosed for forming fine photoresist patterns on semiconductor devices using a modified, two-step dry develop process using a fluorine-containing gas to produce hydrophobic SiOx passivation layers on the sidewalls of the photoresist patterns. These passivation layers increase the structural stability of the fine photoresist patterns and prevent moisture within an air from cohering on the photoresist patterns when the semiconductor substrate is subsequently exposed to the air. Accordingly, the present invention improves the processing margins for very high aspect ratio photoresist patterns resulting in reduced rework and increased yield on very highly integrated semiconductor devices.

Abstract: A method of forming polycrystalline silicon germanium gate electrode is disclosed. The method include the steps of forming gate insulation layer on a substrate, forming a polycrystalline silicon layer on the gate insulation layer and making a plasma doping of germanium to the polycrystalline silicon layer. Generally, boron is doped to the polycrystalline silicon after the step of the plasma doping of germanium. The process of plasma doping of germanium comprises the step of forming germanium contained plasma and enhancing bias electric potential to substrate for the formulated germanium plasma to be accelerated and injected to the polycrystalline silicon layer revealed. If the present invention is applied to CMOS transistor device, doping mask for the germanium plasma doping can be used.

Abstract: A logic circuit is formed of an I2L cell structure in which a difference of switching speeds at every collectors in a multi-collector structure is small. In a semiconductor device in which an integrated injection logic cell including a constant current source transistor and a switch transistor is formed on a common semiconductor substrate, a first semiconductor layer (13) doped with a first conductivity type impurity and a second semiconductor layer (19) doped with a second conductivity impurity are electrically isolated from each other on a semiconductor substrate. A plurality of collector electrodes of the switch transistor and a plurality of collector regions (20) based on diffusion of impurity are formed by the second semiconductor layer (19). The first semiconductor layer (13) includes a base electrode deriving portion, and a direct contact portion which directly contacts with the semiconductor substrate between a plurality of collector regions (20).

Abstract: A method of fabricating, from a first semiconductor substrate having two parallel main surfaces, a system including an islet of a semiconductor material surrounded by an insulative material and resting on another insulative material includes forming a layer of a first insulative material, and forming on the top main surface of the first semiconductor substrate a thin semiconductor layer forming the islet of semiconductor material. The thin semiconductor layer can be selectively etched relative to the first semiconductor substrate. A layer of a second insulative material is formed on exposed surfaces of the islet of semiconductor material and the thin semiconductor layer. The method further includes removing the first semiconductor substrate.

Abstract: A method of fabricating a semiconductor device includes the steps of: forming a well of first conductivity type and well of second conductivity type in a substrate; forming a field oxide layer and gate oxide layer on the substrate; forming first and second polysilicon layers on the field oxide layer and gate oxide layer, the first polysilicon layer being doped with impurities of second conductivity type, the second polysilicon layer being doped with impurities of first conductivity, the first and second polysilicon layers coming into contact with each other; patterning the first and second polysilicon layers to be isolated from each other, to thereby forming first and second gates; and forming a conductive layer between the first and second gates. Accordingly, isolation of N-type and P-type polysilicon layers from each other, and patterning of them for the purpose of forming a gate are carried out using one mask, effectively simplifying the etching process during a gate patterning process.

Abstract: This invention is a method comprising preparing a sample by coating a thin film of a precursor material, which is free of fluorescent probe molecules onto a substrate and subjecting the precursor material to conditions to attempt to cause cure of the precursor to an organic, aromatic, polymer having a dielectric constant of less than 3.0, exposing the sample to radiation having a wavelength in the range of 200 to 500 nm, detecting a resulting emission of radiation, and comparing the emission to the emission for a known cured, non-oxidized standard for the polymer.

Abstract: A method of dividing a semiconductor wafer of which the surface has a plurality of chips sectioned by streets, into individual chips, characterized in that it comprises a scribing step in which division guide lines are formed by drawing scribed lines along the streets on the surface of the semiconductor wafer, a tape sticking step in which a tape is stuck onto the surface having the division guide lines formed thereon, of the semiconductor wafer, and a back surface cutting step in which cutting grooves are formed in the back surface, to which the tape is stuck, of the semiconductor wafer such that a bit of uncut portions are left along the division guide lines.

Abstract: Fabricating thin film transistors. A gate electrode is formed on a substrate. A gate oxide film is then formed on the gate electrode. A polysilicon layer is deposited on the gate oxide film. An impurity ion is implanted into the polysilicon layer to control a threshold voltage of the polysilicon layer. A mask is formed on the polysilicon layer above the gate electrode, having the same width as the gate electrode. A second impurity ion is implanted into the exposed portion of the polysilicon layer using the mask, to form a lightly doped offset region on a drain region. The mask is removed. A second mask is formed on the polysilicon layer so as to cover a portion of the gate electrode and the light doped offset region. A Third impurity ion is implanted into the polysilicon layer using the second mask to form source/drain regions. The mask is removed.

Abstract: There is provided a method of forming a fine pattern comprising the steps of: forming a work film to be processed on a substrate; forming a hard mask film which has a different etching rate from the work film and can serve as a mask to the work; forming a first resist pattern on the hard mask film by lithography; forming a hard mask pattern by etching a first section which is not covered with the first resist pattern till the upper surface of the work film is exposed; removing the first resist pattern; forming a second resist pattern on the hard mask pattern by lithography; etching a second section which is not covered with the second resist pattern by isotropic etching; removing the second resist pattern; and etching the work film through the hard mask pattern as a mask, partially subjected to the isotropic etching. This method enables to prevent the whole remaining patterns from shrinking even when fine patterns beyond the resolving power in lithography technologies are formed.

Abstract: A method for manufacturing an aluminum oxide film for use in a semiconductor device which includes the following steps: preparing a semiconductor substrate and setting the semiconductor substrate in a reaction chamber; supplying modified trimethyl aluminum (MTMA) as an aluminum source material into the reaction chamber so that it could be absorbed on the semiconductor substrate; discharging unreacted MTMA or by-product through a first pump by permitting nitrogen gas to flow into the reaction chamber and purging the chamber for vacuum status; supplying an oxygen source into the reaction chamber so that it could be absorbed on the semiconductor substrate; and discharging an unreacted oxygen source or by-product through a second pump by permitting nitrogen gas to flow into the reaction chamber and purging the chamber for vacuum status.

Abstract: A method for restoring an eroded portion in an exposed upper surface cavity of a metallic element in a microelectronic device, where the metallic element has a hardness, and the metallic element is laterally surrounded by lateral elements, where at least one structure within the lateral elements has a hardness that is greater than the hardness of the metallic element. A precursor material is deposited in at least the cavity of the upper surface of the metallic element. The precursor material is deposited to a thickness that at least fills the cavity of the upper surface of the metallic element. The precursor material has a hardness that is less than the hardness of the at least one structure within the lateral elements. The precursor material is removed as necessary from the lateral elements, and the precursor material is planarized. Only the precursor material within the cavity of the upper surface of the metallic element is selectively replaced with a desired material.

Abstract: A method of manufacturing a MOSFET semiconductor device comprises providing a gate electrode having first and second opposing sidewalls over a substrate having source/drain regions; providing a gate oxide between the gate electrode and the substrate; forming first and second sidewall spacers respectively disposed adjacent the first and second sidewalls; implanting nitrogen into the sidewall spacers; forming a nickel layer; and forming nickel suicide layers disposed on the source/drain regions and the gate electrode. The nickel silicide layers are formed during a rapid thermal anneal at temperatures from about 380 to 600° C. The nitrogen implantation process is a plasma treating in a plasma-enhanced chemical vapor deposition chamber, and the nickel deposition is performed in a physical deposition chamber. Also, the implantation process and the formation of the nickel layer are sequentially performed without removal from a non-oxidizing atmosphere.

Abstract: A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.

Abstract: A capacitor having a storage electrode and a plate electrode, wherein both are made of metal or metal oxide, a high dielectric film formed between the electrodes, and a method of manufacturing the same. A diffusion prevention film is found at the side of the storage electrode and on the plate electrode. Therefore, the invention prevents deterioration of the property in the dielectric film due to penetration of hydrogen ions during a subsequent thermal process thereby improving the reliability of a device.

Abstract: A method of fabricating a dual damascene opening in a dielectric layer above a substrate. A first photoresist layer having a first opening therein is formed over the dielectric layer. The first opening exposes the dielectric layer at a position where a via is desired. A buffer layer is formed over the first photoresist layer. A second photoresist layer having a second opening is formed over the buffer layer. The second opening exposes the area where a conductive wire is desired. The first opening and the second opening together form a metallic interconnect structure. Using the first and the second photoresist layer as a mask, a dual damascene structural opening that includes a via opening and a conductive wire trench is formed in the dielectric layer.

Abstract: Conductive lines, such as co-axial lines, integrated circuitry incorporating such conductive lines, and methods of forming the same are described. In one aspect, a substrate having an outer surface is provided. A masking material is formed over the outer surface and subsequently patterned to form a conductive line pattern. An inner conductive layer is formed within the conductive line pattern, followed by formation of a dielectric layer thereover and an outer conductive layer over the dielectric layer. Preferred implementations include forming the inner conductive layer through electroplating, or alternatively, electroless plating techniques. Other preferred implementations include forming the dielectric layer from suitable polymer materials having desired dielectric properties. A vapor-deposited dielectric layer of Parylene is one such preferred dielectric material.

Abstract: Methods are provided for conductively contacting an integrated circuit, including a plurality of spaced apart lines thereon, using a dummy dielectric layer. A dummy dielectric layer is formed between first selected ones of the spaced apart lines. An interdielectric layer is formed between second selected ones of the spaced apart lines that are different from the first selected ones of the lines. The interdielectric layer has a lower etch rate than the dummy dielectric layer with respect to a predetermined etchant. The dummy dielectric layer is etched with the predetermined etchant, to remove at least some of the dummy dielectric layer between the first selected ones of the spaced apart lines. A conductive layer is formed between the first selected ones of the spaced apart lines from which at least some of the dummy dielectric layer has been removed, to electrically contact the integrated circuit between the first selected ones of the spaced apart lines.

Abstract: A method for reducing surface defects of a semiconductor substrate comprising selectively etching an insulation film formed on a semiconductor substrate and forming a contact hole, forming a conductive layer in a contact hole and on the upper surface of the insulation film, performing a Chemical Mechanical Polishing process on the conductive layer to expose the upper surface of the insulation film and forming a conductive layer plug in the contact hole, forming an oxide film on the upper surface of the conductive plug, and washing the conductive layer plug and the surface of the insulation film. In order to reduce surface defects of a semiconductor substrate, an oxide film is formed on the surface of the semiconductor substrate during the Chemical Mechanical Polishing process or after the Chemical Mechanical Polishing process, so that the efficiency of the post-washing process is heightened and the surface defects of the substrate is reduced.