Abstract: A data processing apparatus having a subroutine processing function which saves and resumes the contents of general registers at the time of shifting into a subroutine or at the time of resume processing. Three layers of general registers are provided, each layer being comprised of a group of registers of a plurality of stages. The layers are connected in the form of a ring while coupling the corresponding registers of neighboring layers for each bit, so that the data can be batchwisely transferred in both directions. When shifted into a subroutine, the contents of a group of registers of the layer that had been used before the shifting are batchwisely transferred to a group of registers of a neighboring layers. The subroutine to which the operation is shifted uses the layer to which the data are transferred.

Abstract: A system for facilitating the mass duplication of flexible diskettes of the type used to store programs and related data for use with word processors, computer systems, etc. A microprocessor-controlled base station, including a Kopy Module and two associated manual modules, is coupled by means of a daisy-chained bidirectional data Way to a plurality of slave stations. The Kopy Module may be used to store a plurality of possible diskette formats as well as operator-introduced copy and duplicating instructions. Blank diskettes are fed into the slaves and the blank diskettes are formatted in accordance with information supplied by the master. An especially designed translator contained within the Kopy Module allows diskettes bearing all of the commonly used data encoding techniques to be replicated. In another mode of operation, diskettes with unknown formats are analyzed, deciphered and stored for later use.

Abstract: A programmable, high speed, single chip microcomputer includes 4K of RAM, ROM, registers and an ALU. Program can be stored in the on-chip RAM. The first local variable of each process to be executed is a workspace pointer (WPTR), and each process has a respective workspace identified by its WPTR. For each process, addressing of other variables is relative to the current WPTR, which is stored in a workspace pointer register (WPTR REG). Instructions are constant bit size, having a function portion and a data portion loaded, respectively, into an instruction buffer (IB) and an operand register (OREGTR). Memory address locations are formed by combining the contents of the workspace pointer register and the operand register, or the contents of the A Register and the operand register. A set of "direct functions" obtains data from OREG. "Indirect functions" use the OREG contents to identify other functions, obtaining data from registers other than the operand register.

Abstract: A data transmission control device for controlling the data transfer between two memory means on the basis of an instruction from a processor is disclosed in which the instruction from the processor is decoded, a transfer request is issued to each memory means a plurality of times, depending upon a transfer unit indicated by the decoded instruction and an access unit of each memory means, a data buffer is provided between the memory means to temporarily store data whichis transferred from one of the memory means to the other memory means, and the issue of a transfer request to each memory means is allowed or stopped in accordance with the quantity of data stored in the data buffer.

Abstract: A memory storage scheme permitting storage of characters in one of several orientations in response to selected applied addresses, including a plurality of random access memory (RAM) chips organized into RAM SETS, each set including N.sub.B devices where N.sub.B equals the number of bits in a character, each device being organized as N.sub.R +1 bits where N.sub.R is the number of bits stored in each device; each RAM SET describing R adjacent rows of bit map, each row containing KN.sub.B +1 bits.

Abstract: A data structure for use in a document processing system corresponds to a document comprised of one or more Pages. Each Page is subdivided into one or more nonoverlapping Areas, each Area in turn being comprised of one or more types of Layers. Each Layer type is expressive of a particular type of information such as text or graphics information. Different Layer types may be superimposed to comprise the contents of an Area.

Abstract: Disclosed is a method for causing an existing display and/or printing mode in a computer or the like to be preserved in sheltering areas located in memory upon commencement of an interrupt task. After completing such an interrupt task, the present invention causes use of the sheltered mode to be resumed. The present invention correctly preserves the originally existing display and/or printing mode until after completion of an externally generated interrupt task, thus effectively eliminating the undesirable process that is otherwise needed for reactivating the original mode.

Abstract: There is provided a data processing circuit for processing symbol data read from a disc of a digital audio system such as a DAD player. Each of the symbol data read from the disc is first stored into a buffer register and then transferred therefrom to a symbol memory in accordance with internal pulse signals, and the number of the pulse signals generated during a period required to process one frame of symbol data is greater than that of symbol data contained in one frame of symbol data. An address data for addressing a desired area of the symbol memory is formed by adding a reference address data generated by counting the internal frame synchronization signals to a relative address data generated by adding together a specific pair of addressing data read out from an address memory, the address memory storing a plurality of groups of addressing data to be used in accordance with each mode of operation of this circuit.

Abstract: An address environment storage unit for a stack-oriented data processor for operating in data sets arranged as structured blocks, or nested pushdown stacks. The address environment storage employs a plurality of sets of display registers such that the current set of display registers does not have to be updated each time the processor moves to a different area of data in memory. The programmer only needs to provide a designation of a lexical level in a particular stack and the offset value from the base of the particular activation record in that stack for addition to obtain actual memory address. When the processor executes a procedure enter operator that calls for a new section of memory in which to operate, a display pointer is changed to point to the set of display registers provided for accessing that new area of memory.

Abstract: A programmable, high speed, single chip microcomputer includes 4K of RAM, ROM, registers and an ALU. Program can be stored in the on-chip RAM. The first local variable of each process to be executed is a workspace pointer (WPTR), and each process has a respective workspace identified by its WPTR. For each process, addressing of other variables is relative to the current WPTR, which is stored in a workspace pointer register (WPTR REG). Instructions are constant bit size, having a function portion and a data portion loaded, respectively, into an instruction buffer (IB) and an operand register (OREGTR). Memory address locations are formed by combining the contents of the workspace pointer register and the operand register, or the contents of the A Register and the operand register. A set of "direct functions" obtains data from OREG. "Indirect functions" use the OREG contents to identify other functions, obtaining data from registers other than the operand register.

Abstract: An apparatus for controlling sequential (DMA) transfers between a plurality of buffer memories and a data translation device. Each buffer has an overrun has an overrun area associated with it. Prior to transfers from the buffers to the data translation device, the buffer memories are first "threaded" together by loading the overrun area of a first buffer with data from the next buffer. During the DMA transfer, when the first buffer becomes empty a request is made to the computer to restart the DMA operation on the next sequential buffer, but while the interrupt is being serviced data is continually being transferred out of the first buffer's overrun area. Alternatively, for transfers from the data translation device to the buffers, after the first buffer is full, an interrupt is generated and incoming data is stored in the first buffer's overrun area while the interrupt is being serviced. After the interrupt is serviced data is stored in the next sequential buffer.

Abstract: A synchronizing circuit synchronizes the asynchronous ready signals for two separate microprocessor subsystems that are running synchronously as part of a fault tolerant computer system. Duplicated synchronization circuits, confined in a master-slave arrangement, are utilized with the duplicate microprocessors. Storage and gating circuitry are used to provide the precise timing signals required for such synchronization.

Abstract: In a digital computing system such as the Digital Equipment Corporation's VAX computer system which uses the VMS operating system in which terminal devices are connected to the system through terminal dependent device drivers coupled to terminal independent device drivers so that the operating system of the computer system need not be modified each time a terminal device is added or subtracted, a system and method is provided for effectively paralleling an auxiliary terminal with a selected terminal of the system so that the selected terminal can be monitored for instruction, security, audit, or other purposes, by creating a user controlling driver and a user controlling device coupled thereto, and coupling the user controlling driver and user controlling device combination between the terminal independent device driver and the terminal dependent device driver associated with the terminal device to be paralleled so that the output of the terminal independent device driver intended for the terminal dependent d

Abstract: A memory control apparatus for a data processor using a virtual memory technique includes two cache memories one for storing a portion of the instructions located in the main memory (MMU), the other for storing a portion of the operand data located in main memory. A separate translation look aside buffer (TLB) is connected to each cache memory, with the TLB connected to the cache memory storing instructions operating to translate logical addresses to real addresses in the MMU storing instructions, while the TLB connected to the cache memory storing operand data operating to translate logical addresses to real addresses in the MMU storing operand data.

Abstract: A data storage system utilizing a technique for compressing input data from cross-correlated sets of parameter values. The system dynamically allocates storage space based upon values of the input data. In systems where the multivalues parameters are grouped about a mean value, the data allocation techniques saves considerable memory area over a memory allocation for all possible values. A first embodiment uses one or more pointer matrix memories which store the addresses of blocks of counter locations. The first occurrence of a parameter set causes the assignment of a counter location for that set in a memory block whose address is stored in a pointer called by the occurrence of the set. Upon each subsequent occurrence of a set, the assigned counter location for the set is called through the pointer and incremented to maintain an accurate account of the frequency of the set occurrence.

Abstract: An intelligent interface arrangement is provided for controlling operation of peripheral devices including a video device and a random access slide projector from a computer. The computer via the interface arrangement also controls the audio and video inputs to the system monitor for the selection of either audio channel from the video device, no audio, or mixed audio. The video control includes selection of video from the video device or computer. The computer addresses the interface arrangement with a predetermined unique address code. The address also includes the category of video device to be controlled. Each command sequence from the computer to the interface arrangement includes a start of command byte, one or more command bytes and an end of command byte. Each communication command sequence also includes a video-audio device command byte for selection of desired audio and video modes.

Abstract: A method and apparatus creates part program data by entering coordinates which specify points on a drawing placed on a tablet. The method includes entering coordinate values of points on the drawing by designating the points, and entering information for specifying the part program data to be created. The part program data is created using said information and the coordinates of the points. The part program data can be created simply in a short period of time without requiring special skills.

Abstract: In order to synchronize data signals transferred from a source unit to a destination unit, a clock signal is transmitted from the destination unit to the source unit and transmission of data is effected under control of the received clock signal. The received clock signal is retransmitted back to the destination unit with the trasmitted data and is used to register receipt of the data.

Abstract: A sequence program for a system to be sequence-controlled is divided into a plurality of divisional programs, which are stored in a program memory of a sequence processor. A main program including a plurality of instruction blocks is read out from the system under control and the execution or non-execution status of the divisional program for the corresponding instruction block is determined and stored in the program memory of the sequence processor. An address table indicating correspondence between the divisional programs and their top addresses is stored in a data memory of a sequence control processor. The sequence processor cyclically executes the main program, and when it determines the need for execution of the divisional program in a certain instruction block, it issues an interrupt signal including identification information for identifying the corresponding divisional program to the control processor.

Abstract: A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations is disclosed. An instruction fetch unit includes an instruction buffer for prefetching and retaining instructions from a memory and alignment means for aligning the instructions from the instruction buffer such that the instruction includes at least one operand specifier in one machine cycle, and provides it to a decoding unit. The decoding unit includes an operation code decoder and two operand specifier decoders to decode two operand specifiers simultaneously when the last operand specifier is a register designation mode. Each of the units executes instructions in a pipelined fashion and processes operands in a pipelined fashion.