Abstract: A 32-bit central processing unit (CPU) having a six-stage pipeline architecture with an instruction and data cache memory and a memory management units, all provided on a single, integrated circuit (I.C.) chip. The CPU also contains means for controlling the operation of a separate I.C. chip co-processor that is dedicated to performing specific functions at a very high rate of speed, commonly called an extended processing unit (EPU). The EPU is provided with interface circuits that generate control signals and communicate them to the controlling CPU.

Abstract: A data base system includes future versions of the data base which are maintained currently in response to orders for future execution. All transactions against the data base are time stamped to assure access to the proper version of the data base. Information concerning the various versions are stored as delta nodes or lists. The application of this data base system to the assignment of outside plant telephone facilities to telephone subscribers is also described.

Abstract: In a data handling system having one or more processors, a cache memory associated with each processor and a main memory unit, each cache memory is divided into an equal number of portions, and the main memory is divided into a corresponding number of portions. A data transfer bus is provided between each group of cache memory portions and the corresponding portion of main memory such that each group of cache memory portions corresponds to only a portion of main memory. Each data transfer bus in independently controlled such that the rate of data transfers for the system as a whole is increased.

Abstract: A data processing system having a channel processing device provided with an input/output device which requires input/output interrupt. The channel processing device responding to a request for input/output interrupt, propagating the request for input/output interrupt to a central processing unit, and reporting the state of the input/output device to the central processing unit.

Abstract: A microprocessor system includes a CPU device with on-chip or off-chip memory, and data and control busses for accessing memory and/or peripherals. The peripheral circuitry includes one or more channels for input and/or output of data, wherein various characteristics of the treatment of data in the channel are controlled by the program being executed in the CPU. In one embodiment analog input and output channels are included, and the A-to-D or D-to-A conversion rates are selected by executing a data output instruction by the CPU. The cut-off points of the filters are likewise selected. The A-to-D converter loads a first-in first-out memory which is read by the CPU in burst mode when filled. Likewise, the CPU loads digital data to a first-in first-out memory in the output channel, and then the D-to-A converts at its selected rate.

Abstract: A data processing system for vector processing having a main memory accessible in parallel by a plurality of processors, each processor having a cache memory, wherein, in response to a storage instruction given to the main memory by a processor, a main memory block of a given size (BS) and having a give start address (B) and containing element data spaced at an interelement distance (D) being preempted as a result of the storage instruction, a single block address invalidation takes place at each cache memory previously having data stored at that main memory location, the single block address invalidation corresponding to (BS/D) cache address invalidations, whereby repeated sequential individual cache address invalidation operations for each address in the preeempted block no longer are required.

Abstract: An improved apparatus for shifting the positions of data bits within a word. A plurality of control means are provided, each of which receives a data bit from the word and which controls the direction of shift of the data bit. A plurality of multiplexer means are provided, each associated with one of the control means. The multiplexer means are interconected among one another and receive a data bit from their associated control means for propagation to one of the other multiplexer means, or receives a data bit from another of the control means and provides the data bit to its associated control means. The multiplexer means are interconnected and controlled in such a manner that the number of control signals required to achieve the desired amount of shifting is minimized. In this manner, a simple, less expensive yet high speed position shifting apparatus is obtained.

Abstract: The data transmitter is formed as a memory connected to the bus for storing a channel program containing transfer commands. The control device includes a comparison device and first and second registers connected to the comparison device having mutually correlated register positions marking termination causes. The control device controls the data transfer between the data transmitter and data receiver as a function of the channel program stored in the memory.

Abstract: A large capacity (8 memory banks of 524K error-corrected 36 bit words stored) high performance (latency as low as 240 nanoseconds, 12.8 gigabits/second aggregate data transfer capability with up to 11.4 gigabits/second utilized) pipelined (8 deep request pipeline) random access memory store simultaneously (to the limit of bank addressing conflicts) services intermixed requests from an internal exerciser plus ported requestors (up to 10) of plural types (3 types), which requestors are not of the same interface cycle time (30 nsec vs. 60 nsec). Furthermore, to such nonuniform interface cycle times, the bit-width of the data transfer interfaces (ports) to the requestors of plural types is also not uniform, but is actually wider (4 interface words of 36 bits each=144 bits) to faster (30 nanosecond) requestors than is that data transfer bit-width (2 interface words=72 bits) to slower (60 nsec) requestors.

Abstract: A control program signal demodulating device comprises a control program demodulator for obtaining a demodulated output of a control program signal from a signal which is reproduced from a rotary recording medium which is recorded with at least the control program signal together with a video signal, where the control program signal indicates a control program including input and output commands and internal processing commands of an external device such as a computer which has a discriminating function and is coupled to a player which plays the rotary recording medium, a memory circuit for at least temporarily storing the demodulated output of the control program demodulator and producing the stored demodulated output, a selecting circuit for selectively producing data received from the memory circuit in response to a transmission request, an interface circuit for transmitting the data which is produced from the selecting circuit to the external device, and for receiving one or a plurality of control command

Abstract: The invention provides a device and method for data processing.

Abstract: A circuit arrangement for supplying interrupt requests signals from a peripheral unit to a central processing unit of a computer system over a common control line, without a priority scheme. A blocking circuit is provided such that the first interrupt signal on the common control line blocks any further interrupt signals on that line until the interrupt has been processed. Since no further interrupts are possible, the interrupt acknowledged signal from the central processing unit need not contain the address of the external unit having requested the interrupt nor need there be provided a circuit to process the interrupt acknowledge signal in the peripheral unit. An interrupt signal present on the common interrupt line blocks generation of subsequent interrupt signals from reaching the common interrupt line by a combination of the two interrupting switches together with a delay after the first switch.

Abstract: This invention relates to a register and more specifically to register control in a data processing system. In general, a number of control registers are theoretically required that is less than the maximum number which can be designated, and only the required number of registers are mounted as hardware. In order to add functions or to provide compatibility with other systems, it is sometimes required to use a register that is not mounted as hardware, or to use the registers mounted as hardware for conflicting purposes. Virtual registers are accordingly provided for at address locations in the memory of the processing system. However, if only the registers to be added are thusly provided for in the memory, the instructions must be executed by distinguishing between register access and memory access, in accordance with register number, etc. Thus, this invention provides a number of virtual registers for instance equal to the number that can be designated.

Abstract: A circuit and technique of operation thereof are disclosed for a multimaster CPU system wherein a memory may be accessed during program operation in an average time less than that of the memory access time specification. This technique has particular usefulness in programs contained in relatively slow read-only-memory wherein a significant portion of the addresses related to memory are sequential. In optimum utilization, each master CPU has a dedicated PROM card which can only be enabled by the specified CPU. This configuration prevents additional master CPU's from interfering with the time saving benefits of early memory addressing.

Abstract: A fail-safe 2-out-of-3 selecting facility for a 3-computer system is disclosed which is especially suitable for use together with microprocessors having a large number of outputs. The computers (R1 . . . R3) of the 3-computer system handle the same information in parallel but asynchronously, exchange their results, and compare them. The output buses (A1, A3) of two computers (R1, R3) transfer the results in nonequivalent form, and are connected to two data output channels (AK1, AK2) via separate transfer switches (U1, U2). Depending on the result of the comparisons performed in the computers, the output ports of faulty computers are disconnected and the transfer switches are controlled in such a way that the output port of a faulty computer is disconnected from the associated data output channel, and that the output port (A2) of the third computer (R2) is connected to this channel instead.

Abstract: In a data processing or control system, a method and apparatus for scheduling the sequential processing of actions requested by a series of transaction requests where the execution of two or more sequential processing actions is required to honor each request. A single queue is used to store entries corresponding to the transaction requests. A particular entry is not removed from the queue until all the associated processing actions have been completed. An exemplary queue is used for scheduling the processing actions of a series of transaction request entries, each entry requiring the performance of initial processing and final processing. The queue is controlled by three queue indicators such as pointers.

Abstract: A common memory interfacing circuit and method for coupling a memory to either a synchronous bus or an asynchronous bus. Synchronizing means are provided for synchronizing memory request signals with a local clock when the interfacing circuit is coupled to an asynchronous bus. The interface circuit responds to signals from the memory when internal memory operation has been completed and generates an acknowledge signal to send to the requesting bus. To simplify the common interface circuit, a synchronous protocol for information exchange between system components is made similar to an asynchronous protocol.

Abstract: A high speed, integrated circuit microprocessor includes a microinstruction sequencer for sequentially generating a plurality of N control words per period, each control word having a plurality of M bits. The microsequencer includes a storage register in the integrated circuit, having a plurality of M times N storage locations, for storing a microinstruction containing the N control words. The microsequencer also includes an N bit shift register in the integrated circuit, having N sequential outputs and a clock input with a cycle time equal to 1/N of the period, for propagating a binary bit therethrough to sequentially provide an enabling bit to each of the respective N outputs thereof. A plurality of M logic stages is also included in the integrated circuit, each stage including a plurality of two-input N AND gates. An i.sup.th one of these N AND gates in each stage has a first input connected to an i.sup.

Abstract: An adaptively stretched clock input feature is provided on a natively synchronous DMAC device to make it support data transfers in an asynchronous bus environment. This feature effects adjustment of the DMAC transfer strobe access window as a function of data transfer (DTACK) timing. A late DTACK signal causes stretch of the clock controlled TXSTB transfer strobe to a length which will accommodate worst case memory access conditions of the asynchronous bus structure.

Abstract: A method for Direct (DASD) cache management that reduces the volume of data transfer between DASD and cache while avoiding the complexity of managing variable length records in the cache. This is achieved by always choosing the starting point for staging a record to be at the start of the missing record and, at the same time, allocating and managing cache space in fixed length blocks. The method steps require staging records, starting with the requested record and continuing until either the cache block is full, the end of track is reached, or a record already in the cache is encountered.