Patents Examined by William M. Treat
  • Patent number: 7917735
    Abstract: A data processing apparatus and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in a cache for access by processing circuitry. For a first set of instructions, each instruction comprises a plurality of instruction portions, and the pre-decoding circuitry generates a corresponding pre-decoded instruction comprising a plurality of pre-decoded instruction portions.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: March 29, 2011
    Assignee: ARM Limited
    Inventor: Peter Richard Greenhalgh
  • Patent number: 7917736
    Abstract: A synchronization mechanism is used to synchronize events across multiple execution pipelines that process transaction streams. A common set of state configuration is included in each transaction stream to control processing of data that is distributed between the different transaction streams. Portions of the state configuration correspond to portions of the data. Execution of the transaction streams is synchronized to ensure that each portion of the data is processed using the state configuration that corresponds to that portion of the data. The synchronization mechanism may be used for multiple synchronizations and when the synchronization signals are pipelined to meet chip-level timing requirements.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: March 29, 2011
    Assignee: NVIDIA Corporation
    Inventors: Mark J. French, Steven E. Molnar
  • Patent number: 7890733
    Abstract: A data processor comprises a plurality of processing elements (PEs), with memory local to at least one of the processing elements, and a data packet-switched network interconnecting the processing elements and the memory to enable any of the PEs to access the memory. The network consists of nodes arranged linearly or in a grid, e.g., in a SIMD array, so as to connect the PEs and their local memories to a common controller. Transaction-enabled PEs and nodes set flags, which are maintained until the transaction is completed and signal status to the controller e.g., over a series of OR-gates. The processor performs memory accesses on data stored in the memory in response to control signals sent by the controller to the memory. The local memories share the same memory map or space. External memory may also be connected to the “end” nodes interfacing with the network, eg to provide cache.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: February 15, 2011
    Assignee: Rambus Inc.
    Inventor: Ray McConnell
  • Patent number: 7890740
    Abstract: A processor comprises a first mode of operation and a second mode of operation. A state of the processor in the first mode of operation comprises a first plurality of variables. The first plurality of variables comprises a return address. A state of the processor in the second mode of operation comprises a second plurality of variables in addition to the first plurality of variables. The processor is configured to perform, in case of an interrupt or exception occurring during the second mode of operation, the steps of saving the second plurality of variables and the return address to a buffer memory, replacing the return address with an address of a trampoline instruction, and switching into the first mode of operation. These steps are performed independently of an operating system.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: February 15, 2011
    Assignee: Globalfoundries Inc.
    Inventor: Uwe Kranich
  • Patent number: 7886135
    Abstract: Instructions asserted in a microprocessors instruction pipeline (3) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (5) that is synchronized to the instruction pipeline. At the execution stage, the control information is interpreted and appropriate action taken. The control information may indicate that the instruction has been reasserted (asserted again following an initial assertion) and may also indicate the number of times that the instruction has been consecutively asserted in the instruction pipeline. Applied to unaligned memory operations, in which a memory atom is asserted twice, the control information indicates which part of the unaligned data is to be fetched each time the atom is executed.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: February 8, 2011
    Inventors: Brett Coon, Godfrey D'Souza, Paul Serris
  • Patent number: 7886129
    Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: February 8, 2011
    Assignee: MIPS Technologies, Inc.
    Inventors: Lawrence Henry Hudepohl, Darren Miller Jones, Radhika Thekkath, Franz Treue
  • Patent number: 7874009
    Abstract: Provided is a data processing device that can prevent data used by a program from being used by another program in an unauthorized manner, regardless of the quality of the programs. The data processing device includes: a CPU 0201 for executing programs; and an unauthorized operation prevention circuit 0105 that prevents unauthorized accesses to data between programs. An unauthorized operation prevention control unit 0106, which operates in the protected mode and controls the circuit 0105, judges whether or not to permit a program B 0103 that runs in the normal mode to use a memory area that is used by a program A 0102 that runs in the normal mode, based on a function flag assigned to the program B 0103. If it judges to permit, the circuit 0105 is set so that the program B 0103 can use the memory area.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: January 18, 2011
    Assignee: Panasonic Corporation
    Inventor: Kouichi Kanemura
  • Patent number: 7853860
    Abstract: A programmable signal processing circuit has an instruction processing circuit (23, 24, 26), with an instruction set that comprises a depuncture instruction. The instruction processing circuit (23, 24, 26) forms the depuncture result by copying bit metrics from a bit metrics operand and inserting one or more predetermined bit metric values between the bit metrics from the bit metric operand in the depuncture result. The instruction processing circuit (23, 24, 26) changes the relative locations of the copied bit metrics with respect to each other in the depuncture result as compared to the relative locations of the copied bit metrics with respect to each other in the bit metric operand, to an extent needed for accommodating the inserted predetermined bit metric value or values.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: December 14, 2010
    Assignee: Silicon Hive B.V.
    Inventors: Paulus W. F. Gruijters, Marcus M. G. Quax
  • Patent number: 7844796
    Abstract: A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: November 30, 2010
    Inventors: Martin Vorbach, Alexander Thomas
  • Patent number: 7818540
    Abstract: A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: October 19, 2010
    Assignee: Broadcom Corporation
    Inventors: Stephen Barlow, Neil Bailey, Timothy Ramsdale, David Plowman, Robert Swann
  • Patent number: 7802252
    Abstract: A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: September 21, 2010
    Assignee: International Business Machines Corporation
    Inventors: William J. Armstrong, Richard L. Arndt, Michael J. Corrigan, Giles R. Frazier, Timothy R. Marchini, Cathy May, Naresh Nayar, John T. O'Quin, II
  • Patent number: 7797513
    Abstract: A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are processed in a round robin fashion. When a particular packet is done processing at a particular stage, it may pass another packet whose processing is not complete, and move to a next stage. In another embodiment, a packet is processed until a conditional branch instruction or any other instruction causing a potential stall is encountered. If such an instruction is encountered, a next available packet is selected and processed instead of wasting processing cycles during the stall, or proceeding with the processing of the current packet based on a predicted result. The sub-processor resumes processing of the packet once the stall is over.
    Type: Grant
    Filed: July 3, 2006
    Date of Patent: September 14, 2010
    Inventors: Werner Van Hoof, Jerrold Wheeler, Mathieu Tallegas
  • Patent number: 7788471
    Abstract: A system and method for performing vector arithmetic is disclosed. The method includes loading two operand vectors, each composed of a number of vector elements, into two storage locations. A selected arithmetic operation is performed on the operand vectors to produce a result vector having the number of vector elements. Each vector element of the result vector is associated with an arithmetic logic cell that has a first input that can receive any vector element from the first vector and a second input that can receive any vector element from the second vector. Accordingly each vector element of the result vector is a function of any two individual vector elements of the operand vectors. By applying the operand vector elements to the appropriate arithmetic logic cells, and by selecting the appropriate arithmetic operation, complex vector operations can be performed efficiently.
    Type: Grant
    Filed: September 18, 2006
    Date of Patent: August 31, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Chengke Sheng
  • Patent number: 7779233
    Abstract: A system and computer-implementable method for implementing software-supported thread assist within a data processing system, wherein the data processing system supports processing instructions within at least a first thread and a second thread. An instruction dispatch unit (IDU) places the first thread into a sleep mode. The IDU separates an instruction stream for the second thread into at least a first independent instruction stream and a second independent instruction stream. The first independent instruction stream is processed utilizing facilities allocated to the first thread and the second independent instruction stream is processed utilizing facilities allocated to the second thread.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: August 17, 2010
    Assignee: International Business Machines Corporation
    Inventors: Hung Q. Le, Dung Q. Nguyen
  • Patent number: 7779238
    Abstract: A system and method for precisely identifying an instruction causing a performance-related event is disclosed. The instruction may be detected while in a pipeline stage of a microprocessor preceding a writeback stage and the microprocessor's architectural state may not be updated until after information identifying the instruction is captured. The instruction may be flushed from the pipeline, along with other instructions from the same thread. A hardware trap may be taken when the instruction is detected and/or when an event counter overflows or is within a given range of overflowing. A software trap handler may capture and/or log information identifying the instruction, such as one or more extended address elements, before returning control and initiating a retry of the instruction. The captured and/or logged information may be stored in an event space database usable by a data space profiler to identify performance bottlenecks in the application containing the instruction.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: August 17, 2010
    Assignee: Oracle America, Inc.
    Inventors: Nicolai Kosche, Gregory F. Grohoski, Paul J. Jordan
  • Patent number: 7779230
    Abstract: Distant parallelization of sequential programs is obtained by making parallelization decisions at the boundaries between program methods (e.g., functions and sub-routines). Experimentation suggests that such a partitioning allows for large-scale parallelization without data flow conflicts.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: August 17, 2010
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Saisanthosh Balakrishnan, Gurindar Singh Sohi
  • Patent number: 7779234
    Abstract: The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thread of the microprocessor is in a sleep mode. When load lookahead mode is activated, the fixed point unit copies the content of one or more architected facilities from an active thread to corresponding architected facilities in the first inactive thread. The load-store unit performs at least one speculative load in load lookahead mode and writes the results of the at least one speculative load to a duplicated architected facility in the first inactive thread.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: August 17, 2010
    Assignee: International Business Machines Corporation
    Inventors: James W. Bishop, Hung Q. Le, Dung Q. Nguyen, Wolfram Sauer, Benjamin W. Stolt, Michael T. Vaden
  • Patent number: 7774583
    Abstract: A processing bypass register file system and method are disclosed. In one embodiment a processing bypass register file includes a rotating head pointer, and a plurality of write ports, storage cells and read ports. The write ports receive processing result information. The head pointer identifies which entries are written by the write ports. The plurality of cells store the processing result information. The read ports forward results to the processing data path, and to an architectural register file for retirement.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: August 10, 2010
    Inventors: Parag Gupta, Alexander Klaiber, James Van Zoeren
  • Patent number: 7765389
    Abstract: Exception handling is simulated. An exception simulator is employed to simulate exceptions generated from routines simulating operations. The exception simulator provides an indication of the exception and invokes an interruption, when appropriate. The exception simulator includes an instruction invoked to handle the exception and any interruption.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: July 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: Shawn D. Lundvall, Ronald M. Smith, Sr., Phil C. Yeh
  • Patent number: 7747840
    Abstract: Methods for latest producer tracking in a processor. In one embodiment, the method includes the steps of (1) writing a physical register identification value in a first register rename map location specified by a first instruction, (2) writing a first in-register status value in a second register rename map location specified by the first instruction, (3) writing a producer tracking status value at a producer tracking map location specified by the physical register identification value, and (4) modifying, upon graduation of the first instruction, the first in-register status value only if the producer tracking map location stores the producer tracking status value written in step (3). Other methods are also presented.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: June 29, 2010
    Assignee: MIPS Technologies, Inc.
    Inventors: Kjeld Svendsen, Xing Yu Jiang