Patents Examined by William Powell
  • Patent number: 6645863
    Abstract: The invention provides a method of manufacturing a semiconductor device which can reduce or prevent abrasive material from remaining in an indentation in a surface after a CMP process. After forming a titanium nitride film (5), a tungsten film (6) is formed on an entire surface. The temperature is set at approximately 430° C. for the reaction and, first, 50 sccm of WF6, 10 sccm of SiH4 and 1000 sccm of H2 are used in the atmosphere of 30 Torr of Ar, N2 so as to form a seed layer with a film thickness of approximately 100 nm. After that, in the atmosphere of 80 Torr of Ar, N2, 75 sccm of WF6 and 500 sccm of H2 are used as a reactive gas so as to layer a film with a thickness of approximately 300 nm. The tungsten film (6) has grains (6a) in a pillar form of which the grain diameter is small to the degree that the abrasive material (50) used in the CMP process does not easily become caught in the gaps between the grains.
    Type: Grant
    Filed: November 7, 2001
    Date of Patent: November 11, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroki Takewaka, Takao Kamoshima, Junko Izumitani
  • Patent number: 6641746
    Abstract: An integrated metrology and lithography/etch system and method (10) for micro-electronics device manufacturing. A process control neural network (30) is used to develop an estimated process control parameter (32) for controlling an etching process (28). The process control neural network is responsive to a multi-parameter characterization of a patterned resist feature MPC(PR) (16) developed on a substrate. The process control parameter is used as a feed-forward control for the etching process to develop an actual final mask feature. A multi-parameter characterization of the actual final mask feature MPC(HM) (36) is used as an input to a training neural network (40) for mapping to an ideal process control parameter. The ideal process control parameter is compared to the estimated control parameter to develop an error parameter (46), which is then used to train the process control neural network.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: November 4, 2003
    Assignee: Agere Systems, Inc.
    Inventors: Erik Cho Houge, John Martin McIntosh, Edward Alios Rietman
  • Patent number: 6638438
    Abstract: A PC board micro hole processing method using plasma technique to etch the substrate of the PC board, and then using chemical etching technique to remove residual material such as glass fibers.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: October 28, 2003
    Assignee: Ulisatera Corporation
    Inventors: Ching-Hua Tsao, Jou-Yuan Tseng, Kang-Tsun Liu
  • Patent number: 6638440
    Abstract: A method for surface marking a solid substrate (1), according to which, during an exposures sequence, said substrate is exposed to coherent monochromatic light (2) in order to strip said substrate over an indented surface (3), wherein the exposure conditions, including duration, are set in order to restrict said indented surface to simple abrasion designed for the bonding of a printing medium, and the exposure sequence is followed by a sequence of projecting in discrete form, during which particles (6) of said printing medium, the deposition of which subsequently defines a printing element (4), are projected in targeted fashion into the indented surface (3, 31). A device for marking a surface of a substrate is also provided.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: October 28, 2003
    Assignee: Becton Dickinson France, S.A.
    Inventor: Jean-Pierre Grimard
  • Patent number: 6632375
    Abstract: Process for the formation of at least one concave relief (124, 145) in a substrate comprising forming at least one embossment of material subject to creep (100) on the substrate (120), —heating of the material subject to creep to a temperature sufficiently high to cause creep of the said material, and—etching of the substrate and the crept material to form relief in the substrate. According to the invention, the crept material is solidified in a state in which it has a concave relief.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: October 14, 2003
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Marc Rabarot, Jean Marty
  • Patent number: 6632744
    Abstract: Densely disposed patterns constituting a semiconductor integrated circuit device are divided into a first mask pattern and a second mask pattern 28B such that a phase shifter S can be disposed, and a predetermined pattern is transferred on a semiconductor substrate by multiple-exposure thereof. The second mask pattern 28B has a main light transferring pattern 26c1, a plurality of auxiliary light transferring patterns 26c2 disposed thereabout, and a phase shifter S disposed in the main light transferring pattern 26c1. The auxiliary light transferring patterns 26c2 are disposed such that respective distances from a center of each thereof to a center of the main light transferring pattern 26c1 are substantially equal. With this arrangement, a densely disposed pattern is transferred with sufficient process transfer margin.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: October 14, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Akira Imai, Katsuya Hayano, Norio Hasegawa
  • Patent number: 6630402
    Abstract: In integrated circuits produced by etching and damascene techniques, it is common for cracking to occur in dielectric material surrounding an interconnect metal layer integrated into the device, presumably as a result of the transfer of stresses from the interconnect metal layer to the surrounding dielectric material. The present invention addresses this problem by providing an interconnect metal layer that comprises rounded comers which are believed to reduce the stresses transferred to a surrounding dielectric layer.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: October 7, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato
  • Patent number: 6630403
    Abstract: Improved methods, compositions and structures formed therefrom are provided that allow for reduction of roughness in layers (e.g., oxide layers) of a planarized wafer. In one such embodiment, improved methods, compositions and structures formed therefrom for reduction of roughness in layers (e.g., oxide layers) of a planarized wafer are used in conjunction with high modulus polyurethane pads. In one embodiment, improved methods, compositions and structures formed therefrom are provided that reduce rough interlayer dielectric (ILD) conditions for a wafer during CMP processing of such a wafer. Embodiments of a method for forming a microelectronic substrate include mixing a surfactant at least 100 parts per million (ppm) to slurries to form a polishing solution.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: October 7, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Stephen J. Kramer, Scott G. Meikle
  • Patent number: 6630409
    Abstract: A method of forming an emitter electrode of a bipolar transistor. The emitter electrode includes a double-layered structure of a polysilicon layer and a refractory metal silicide layer. The method includes the steps of removing a natural oxide film from a surface of a polysilicon layer by a sputter-etching process using inert gas ions in the range of acceleration energy from 5 eV to 50 eV; depositing a refractory metal layer on the surface of the polysilicon layer; and carrying out a heat treatment to cause a silicidation reaction to form a refractory metal silicide layer over the polysilicon layer.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: October 7, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Hiroshi Murase
  • Patent number: 6630410
    Abstract: A method for forming an etched feature in a substrate such as an insulator layer of a semiconductor wafer is provided. In one embodiment, the method includes initially etching a substrate layer using a photoresist or other masking layer to form the etched feature (e.g., opening) to a selected depth, and depositing a self-aligning mask layer for a continued etch of the formed feature. In another embodiment of the method, the self-aligned mask is deposited onto a substrate having an etched opening or other feature, to protect the upper surface and corners of the substrate and sidewalls of the feature while the bottom portion of the opening is cleaned or material at the bottom portion of the opening is removed.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: October 7, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Shane J. Trapp, Kevin G. Donohoe
  • Patent number: 6627096
    Abstract: Methods for making a micromachined device (e.g. an microoptical submount) having positive features (extending up from a device surface) and negative features (extending into the device surface). The present techniques locate the postive feature and negative features according to a single mask step. In one embodiment, a hard mask is patterned on top of the device layer of an SOI wafer. Then, RIE is used to vertically etch to the etch stop layer, forming the positive feature. Then, the positive feature is masked, and metal or hard mask is deposited on the exposed areas of the etch stop layer. Then, portions of the device layer are removed, leaving the patterned metal layer on the etch stop layer. Then, the etch stop layer is removed in an exposed area, uncovering the handle layer. Then, the handle layer is etched in an exposed area to form the negative feature.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: September 30, 2003
    Assignee: Shipley Company, L.L.C.
    Inventors: David W. Sherrer, Gregory A. Ten Eyck, Dan A. Steinberg, Neal Ricks
  • Patent number: 6624084
    Abstract: In plasma processing equipment having a vacuum processing chamber, a plasma generation means, a stage for loading a wafer to be processed in the vacuum processing chamber, an opposing electrode having an area almost equal to or wider than the aforementioned wafer which is installed opposite to the stage, and a bias power source for applying a high frequency bias to the wafer, a current path correction means is provided for correcting the current path part in the neighborhood of the outer periphery of the wafer among the high frequency current paths produced by the high frequency bias so as to be directed toward the wafer opposing surface of the opposing electrode.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: September 23, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Maeda, Yutaka Omoto, Ichiro Sasaki, Hironobu Kawahara
  • Patent number: 6623654
    Abstract: In accordance with the objectives of the invention a new method is provided for improving adhesion strength that is deposited over the surface of a layer of copper. Conventional etch stop layers of for instance dichlorosilane (SiCl2H2) or SiOC have poor adhesion with an underlying layer of copper due to poor molecular binding between the interfacing layers. The surface of the deposited layer of copper can be provided with a special enhanced interface layer by using a method provided by the invention. That is pre-heat of the copper layer followed by a pre-cleaning treatment with ammonia (NH3) and N2, followed by forming an adhesive enhanced layer over the copper layer by treatment with N2 or O2 or N2 with alkyl-silane or alkyl silane.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: September 23, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Bi-Trong Chen, Lain-Jong Li, Syun-Ming Jang, Shu E Ku, Tien I. Bao, Lih-Ping Li
  • Patent number: 6624077
    Abstract: A method for forming an optical waveguide includes depositing a cladding material on a first substrate, forming a trench in the cladding material on the first substrate, and filling the trench with a optically conductive core material. The upper surface of the cladding material and the optically conductive core material are then planarized to produce a substantially planar surface. The method further includes depositing a cladding material on a second substrate, forming a mirror image trench into the cladding material on the second substrate, and filling the mirror image trench with the optically conductive core material. The upper surface of the second cladding layer and the core material therein is then planarized. Thereafter, the first substrate is affixed to the second substrate such that the trench and the mirror image trench are in abutment and form a substantially circular optical core.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: September 23, 2003
    Assignee: Applied Materials, Inc.
    Inventor: John M. White
  • Patent number: 6616853
    Abstract: A method is provided for preventing dopant leaching from a doped structural film during fabrication of a microelectromechanical system. A microstructure that includes the doped structural film, sacrificial material, and metallic material is produced with a combination of deposition, patterning, and etching techniques. The sacrificial material is dissolved with a release solution that has a substance destructive to the sacrificial material. This substance also acts as an electrolyte, forming a galvanic cell with the doped structural film and metallic material acting as electrodes. The effects of the galvanic cell are suppressed by including a nonionic detergent mixed in the release solution.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: September 9, 2003
    Assignee: Network Photonics, Inc.
    Inventors: Bevan Staple, David Miller, Lilac Muller
  • Patent number: 6616855
    Abstract: Low K dielectrics, such as porous silica, present a problem during damascene processing in that the trench floor tends to be rough, thus requiring a thicker than desired barrier layer. This problem has been overcome by fully covering the trench floor with a layer of a flowable material following which an etchant is provided that etches both the trench and flowable materials at approximately the same rate. Using this etchant, the trench floor is then uniformly etched until only a small amount of flowable material remains. After removal of any and all remaining flowable material, it is found that the roughness at the trench floor has been reduced by a factor of about 3-5. This allows a barrier layer of normal thickness to be used during the standard copper damascene process without danger of copper leakage. The process is particularly well suited for use with porous silica dielectrics having a dielectric constant less than about 2.5.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: September 9, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chao Cheng Chen, Chen Nan Yeh
  • Patent number: 6613673
    Abstract: A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: September 2, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Pai-Hung Pan, Louie Liu, Ravi Iyer
  • Patent number: 6613588
    Abstract: The present invention is to detect particles suspended in a processing chamber using a single observation window and an optical system formed as a single unit and to provide precise detection of very weak particle-scattered light. When a thin film is being formed on an object to be processed in a processing chamber or if such a thin film is being processed, an optical guide module guides a laser beam from a laser light source separated from a laser illumination/scattered light detection optical system. The laser beam is guided to the laser illumination/scattered light detection optical system. The processing chamber is illuminated by the laser illumination/scattered light detection optical system via an observation window. The illumination light is scattered by particles in the processing chamber. Back-scattered light passing through the observation window is detected by the laser illumination/scattered light detection optical system.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: September 2, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Nakano, Toshihiko Nakata
  • Patent number: 6608359
    Abstract: In a semiconductor device having a front surface where circuits are formed and a back surface, a hemispherical solid immersion lens is formed at the back surface of the semiconductor device in a body with the semiconductor device.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: August 19, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Hideki Kitahata
  • Patent number: 6605538
    Abstract: Provided are methods for forming ferroelectric capacitors, which prevent decreasing ferroelectric characteristics due to the reaction of a ferroelectric layer with hydroxyl group induced from a inter-layer insulating film which will be formed and contacted with the ferroelectric layer after the formation of the ferroelectric capacitor. After a ferroelectric film such as Pb(Zr,Ti)O3 (PZT) is formed, a ZrO2 film, which is insulator and excellent in diffusion barrier characteristics, is formed so as to enclose the entire ferroelectric layer in order to prevent the damage generated by the reaction. The characteristics of the ferroelectric capacitor are enhanced by the invention.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: August 12, 2003
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Kwon Hong