Abstract: The polishing slurry includes polishing particles having a mean particle diameter of less than about 5 &mgr;m. The slurry contains at least about 0.5 total weight percent oxidizer selected from at least one of the group consisting of HNO3, Ni(NO3)2, Al(NO3)3, Mg(NO3)2, Zn(NO3)2 and NH4NO3. A small but effective amount of a co-oxidizer selected from the group consisting of perbromates, perchlorates, periodates, persulfates, permanganates, ferric nitrate, cerium-containing salts, perbenzoic acids, nitrite compounds, perborate compounds, hypochlorite compounds, chlorite compounds and chloride compounds accelerates removal of substrates; and water forms the balance of the aqueous slurry.

Abstract: Deleterious physical sputtering of workpiece layers accompanying removal of photoresist layers from the workpiece by plasma ashing utilizing an active plasma ashing gas such as O2, N2, N2/O2, or H2/N2 gas mixtures admixed with Ar inert carrier gas/diluent, is eliminated, or at least substantially reduced, by replacing the Ar with an inert gas of greater atomic weight, such as Kr or Xe, and supplying a lower level of electrical power to the plasma reactor than when Ar is utilized.

Abstract: In a method of etching a wafer in a plasma etch reactor, the improvement of conducting etching to reduce or eliminate “black silicon” comprising: a) providing a plasma etch reactor comprising walls defining an etch chamber; b) providing a plasma source chamber remote from and in communication with the etch chamber to provide a plasma to the etch chamber, and a wafer chuck or pedestal disposed in the etch chamber to seat a wafer; c) providing a dielectric wall in proximity to and around a periphery of the wafer; d) providing a modification to a lower Rf electrode by interposing conductor means into an extension of Vdc flat sheath boundary relationship to the dielectric wall means and the wafer or in substitution for the dielectric wall; e) forming a plasma within the plasma source chamber and providing the plasma to the etch chamber; and f) supplying Rf energy to the wafer chuck to assist etching of the wafer by forming electric fields between the upper surface of the wafer and the walls of t

Abstract: A substrate having a patterned mask and exposed openings is provided in a process chamber having process electrodes. In a plasma ignition stage, a process gas is provided in the process chamber and is energized by maintaining the process electrodes at a plasma ignition bias power level. In an etch-passivating stage, an etch-passivating material is formed on at least portions of the substrate by maintaining the process electrodes at an etch-passivating bias power level. In an etching stage, the exposed openings on the substrate are etched by maintaining the process electrodes at an etching bias power level.

Abstract: In a process of preparing a via in a semiconductor substrate wafer in which vias are landed on tungsten, and in which resist is stripped using plasma or chemical based processes that do not remove the veils formed during the etch, the improvement of concurrently removing veil material, controlling the interface of the tungsten, and stripping the resist, comprising: a) depositing and patterning tungsten on a substrate; b) depositing an oxide as an interlevel dielectric on the tungsten; c) patterning the oxide using photolithography and a photoresist; d) etching the oxide using a plasma generated etching method in which veils made up of metals, carbon based materials and oxide based materials are formed on the tungsten and sidewalls of the vias; and e) stripping the resist using a dry polymer removal method employing process gases and reducing gases to concurrently cause resist stripping, removal of the veils, and control of the tungsten interface.

Abstract: A method for forming an isolation region on a semiconductor substrate with a high yield, comprising partially covering the surface of a semiconductor substrate with an oxidation inhibitor film, depositing a material for side-wall parts on the oxidation inhibitor film and also on an exposed region of the surface, which is revealed through an opening of the oxidation inhibitor film, to form side-wall parts at the edge portions of the oxidation inhibitor film, then, removing by a plasma etching process the unnecessary portions of said side-wall material deposited on the oxidation inhibitor film and on the exposed region of the substrate and leaving intact the side-wall parts at the edge portions of the oxidation inhibitor film, and cleaning the exposed region on the surface of the semiconductor substrate, revealed through the opening of the oxidation inhibitor film, before subsequent heat treatment to generate a field oxide film.

Abstract: In a semiconductor device having a front surface where circuits are formed and a back surface, a hemishperical solid immersion lens is formed at the back surface of the semiconductor device in a body with the semiconductor device.

Abstract: Disclosed is a method for fabricating a stencil mask for use in electron beam lithography which improves resolution by effectively reducing beam blur resulting from coulomb repulsion effects in the electron beam. The disclosed method includes fabricating a first mask and a second mask that are then aligned and joined to form the final stencil mask. The structure of the second mask limits the number and controls the initial pattern of the electrons that pass through the stencil mask to limit beam blur, narrow the incident energy distribution, and improve the resolution of the final image.

Abstract: A method for controlling the sheet resistance of thin film resistors. The sheet resistance can be inexpensively controlled within a tight tolerance by determining a desired final value for the sheet resistance of thin film resistor material to be deposited on a substrate, depositing the resistor material on the substrate using a deposition process which is consistent enough to achieve a target sheet resistance within a first specified tolerance, the resistor material being deposited to achieve a target sheet resistance which is equal to the desired final value minus the first specified tolerance, and removing a small amount of material from the surface of the deposited thin film resistor material by etching or ion bombardment to raise the sheet resistance to the desired final value within a second specified tolerance characteristic of the removing process where the second specified tolerance is less than the first specified tolerance.

Abstract: An etching method for forming an opening includes providing a substrate assembly having a surface and an oxide layer thereon. A patterned mask layer is provided over the oxide layer exposing a portion of the oxide layer. A plasma including one or more of CxHyFz+ ions and CxFz+ ions and further including xenon or krypton ions is used to etch the oxide layer at the exposed portion to define the opening in the oxide layer while simultaneously depositing a polymeric residue on a surface defining the opening. The etching is continued until the opening in the oxide layer is selectively etched to the surface of the substrate assembly.

Abstract: An etching method capable of obtaining a fine fabricated shape, particularly, a vertical fabricated shape with less bowing upon fabrication of insulation films in the production of semiconductors, the method comprising controlling the incident amount of O, F or N radicals, gas flow rate or consumption amount of O, F and N on the inner wall surface with etching time to suppress excessive O, F and N which become excessive in the initial stage of etching, the method also including control for the flow rate or the consumption amount based on the result of measurement for plasmas during etching so as to obtain a stable etching shape. Since bowing can be reduced upon fabrication of insulation film hole and insulation film while maintaining the etching rate and the selectivity, finer semiconductor device can be produced easily.

Abstract: A method is disclosed for providing a TBC system including grooves or other features between the bond coat/substrate and the ceramic thermally insulating layer. The features are initially provided by selectively removing material to define the features, for example by laser. Any disturbed surface layer, e.g., re-cast material in the case of a laser or plastically worked material in the case of machining, is then chemically removed, leaving the remaining material with a microstructure of a more uniform geometry, and free of disturbed material. The ceramic layer is then applied. TBC systems using the method show improved durability, with lives up to 4× longer than prior TBC systems.

Abstract: A method for manufacturing a contact hole in a semiconductor device which includes the steps of preparing an active matrix provided with a substrate and word lines formed on the substrate, forming an etching barrier layer on the word lines and the substrate, forming an interlayer insulating layer on the etching barrier layer, forming a photoresist pattern on the interlayer insulating layer for defining a contact hole, etching the interlayer insulating layer under conditions of low polymerization until the etching barrier layer on the word lines is exposed, etching the interlayer insulating layer under conditions of high polymerization, and etching the interlayer insulating layer under conditions of low polymerization until the etching barrier layer in a bottom of the contact hole is exposed.

Abstract: The present invention provides a method to make a local interconnect in an embedded memory. The method first involves defining both a memory array area and a periphery circuit area on the surface of a semiconductor wafer. Then, a plurality of gates and lightly doped drains (LDD) are separately formed in the memory array area and in the periphery circuit area. A silicon nitride layer and a dielectric layer are then formed, respectively, on the surface of the semiconductor wafer and on each gate. Next, a plurality of landing via holes and local interconnect holes are separately formed in the dielectric layer in the memory array area and in the periphery circuit area, followed by the filling of an electrical conducting layer in each hole to simultaneously form a landing via and local interconnect. Then, the dielectric layer and a portion of the silicon nitride layer in the periphery circuit area are removed to form a spacer on either side of each gate in the periphery circuit area.

Abstract: A process for the etching of multiple layers of at least two different metals comprisies: forming a resist pattern over a first layer of metal, said resist pattern having a pattern of openings therein, applying a first etch solution onto said resist pattern so that at least some etch solution contacts exposed areas of the first layer of metal, etching away the majority of the depth of the first metal in exposed areas of metal in the first layer of metal, applying a second etch solution onto the resist pattern the second etch solution having a rate of etch towards the first metal as compared to the first etch solution that is at least 20% less than the millimeter/minute rate of etch of the first etch solution at the same etch solution temperature, removing the second etch solution from said resist pattern after at least the first metal layer has been etched sufficiently to expose areas of a second metal layer underlying the first metal layer by forming an etched first metal layer, and applying a third etch so

Abstract: The surface of a semiconductor device is polished by first supplying a polishing pad with a slurry that contains a solvent, abrasive grains, and an additive for making the viscosity of the slurry variable so that the top portion of the polishing pad is soaked with the slurry, then supplying the polishing pad with a viscosity modifier for increasing the viscosity of the slurry and hardening the top portion of the polishing pad soaked with the slurry, and finally polishing the surface of the semiconductor device with the slurry having its viscosity increased and the polishing pad having its top portion hardened.

Abstract: In accordance with the invention, there is provided a chemical-mechanical polishing slurry for polishing a substrate. The slurry is comprised primarily of abrasive particles and an oxidizing agent, wherein the slurry exhibits a stability having a shelf life of at least 30 days.

Abstract: The present invention provides a method for the formation of contact plugs of an embedded memory. The method first forms a plurality of MOS transistors on a defined memory array region and periphery circuit region of the semiconductor wafer. Then, a first dielectric layer is formed on the memory array region, and plurality of landing pads is formed in the first dielectric layer. Next, both a stop layer and a second dielectric layer are formed, respectively, on the surface of semiconductor wafer. A PEP process is then used to form a plurality of contact plug holes in the second dielectric layer in both the memory array region and the periphery circuit region. Finally, a conductive layer is filled into each hole to form in-situ each contact plug in both the memory array region and the periphery circuit region.

Abstract: A method of forming a pattern in a layer of material on a substrate, comprising providing a plurality of spheres, covering the layer on the substrate with the plurality of spheres to form a mask, reducing the diameter of at least one sphere of the plurality of spheres, etching the layer on the substrate using at least one sphere having a reduced diameter as a mask, and etching the substrate.

Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.