Patents Examined by Wilner Jean Baptiste
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First-level integration of second-level thermal interface material for integrated circuit assemblies
Patent number: 11881438Abstract: A second-level thermal interface material (TIM2) that is to couple to a system-level thermal solution is applied to an integrated circuit (IC) assembly comprising an IC die and an assembly substrate prior to the assembly substrate being joined to a host component at the system-level. Challenges associated with TIM2 application may therefore be addressed at a first level of IC die integration, simplifying subsequent assembly and better controlling thermal coupling to a subsequently applied thermal solution. Where a first-level IC assembly includes a stiffener, the TIM may be affixed to the stiffener through an adhesive bond or a fusion bond. After the IC assembly including the TIM is soldered to the host board, a thermal solution may be placed in contact with the TIM. With early application of a solder TIM, a solder TIM may be reflowed upon the IC die multiple times.Type: GrantFiled: January 17, 2020Date of Patent: January 23, 2024Assignee: Intel CorporationInventors: Elah Bozorg-Grayeli, Kyle Arrington, Sergio Chan Arguedas, Aravindha Antoniswamy -
Patent number: 11881502Abstract: A method of manufacturing a semiconductor device includes sequentially stacking a mold layer and a supporter layer on a substrate, forming a plurality of capacitor holes passing through the mold layer and supporter layer, forming a plurality of lower electrodes filling the capacitor holes, forming a supporter mask pattern having a plurality of mask holes on the supporter layer and the lower electrodes, and forming a plurality of supporter holes by patterning the supporter layer. Each of the plurality of lower electrodes has a pillar shape, and each of the mask holes is between four adjacent lower electrodes and has a circular shape.Type: GrantFiled: September 30, 2021Date of Patent: January 23, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Seung Jin Kim, Sung Soo Yim
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Patent number: 11876072Abstract: A method for preparing a semiconductor device includes providing an integrated circuit die having a bond pad. The bond pad includes aluminum (Al). The method also includes etching a top portion of the bond pad to form a recess, and bonding a wire bond to the recess in the bond pad. The wire bond includes copper (Cu).Type: GrantFiled: September 2, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Wei-Zhong Li, Yi-Ting Shih, Chien-Chung Wang, Hsih-Yang Chiu
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Patent number: 11876056Abstract: In some examples, a semiconductor package includes a semiconductor die; a passivation layer abutting a device side of the semiconductor die; a first conductive layer abutting the device side of the semiconductor die; a second conductive layer abutting the first conductive layer and the passivation layer; a silicon nitride layer abutting the second conductive layer, the silicon nitride layer having a thickness ranging from 300 Angstroms to 3000 Angstroms; and a third conductive layer coupled to the second conductive layer at a gap in the silicon nitride layer, the third conductive layer configured to receive a solder ball.Type: GrantFiled: April 30, 2021Date of Patent: January 16, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jonathan Andrew Montoya, Salvatore Franks Pavone
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Patent number: 11876032Abstract: A bond layer including at least one metal region in a plan view is disposed on a surface layer portion of a substrate formed from a semiconductor. A semiconductor element is disposed on the bond layer and includes a first transistor disposed on a first metal region that is a metal region as the at least one metal region of the bond layer and including a collector layer electrically coupled to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. A first emitter electrode is disposed on the emitter layer of the first transistor. A first conductor protrusion is disposed on the first emitter electrode. The thermal conductivity of the semiconductor material of the surface layer portion is higher than that of each of the collector layer, the base layer, and the emitter layer of the first transistor.Type: GrantFiled: October 18, 2021Date of Patent: January 16, 2024Assignee: Murata Manufacturing Co., Ltd.Inventors: Shinnosuke Takahashi, Masayuki Aoike, Masatoshi Hase, Fumio Harima
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Patent number: 11876079Abstract: The provides a method for fabricating a semiconductor device including performing a bonding process to bond a second die onto a first die including a pad layer, forming a through-substrate opening along the second die and extending to the pad layer in the first die, conformally forming an isolation layer in the through-substrate opening, performing a punch etch process to remove a portion of the isolation layer and expose a portion of a top surface of the pad layer, performing an isotropic etch process to form a recessed space extending from the through substrate opening and in the pad layer, conformally forming a barrier layer in the through-substrate opening and the recessed space, and forming a filler layer in the through-substrate opening and the recessed space.Type: GrantFiled: November 24, 2021Date of Patent: January 16, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Shing-Yih Shih
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Patent number: 11862597Abstract: An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.Type: GrantFiled: September 23, 2021Date of Patent: January 2, 2024Assignee: Apple Inc.Inventors: Yikang Deng, Taegui Kim, Yifan Kao, Jun Chung Hsu
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Patent number: 11862481Abstract: Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.Type: GrantFiled: August 30, 2021Date of Patent: January 2, 2024Assignee: Apple Inc.Inventors: Sanjay Dabral, Chi Nung Ni, Long Huang, SivaChandra Jangam
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Patent number: 11854913Abstract: A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit.Type: GrantFiled: August 9, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yang-Che Chen, Wei-Yu Chou, Hong-Seng Shue, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
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Patent number: 11855144Abstract: A semiconductor device comprises a fin disposed on a substrate, a source/drain feature disposed over the fin, a silicide layer disposed over the source/drain feature, a seed metal layer disposed over the silicide layer and wrapping around the source/drain feature, and a metal layer disposed on the silicide layer, where the metal layer contacts the seed metal layer.Type: GrantFiled: June 21, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Jia-Chuan You, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
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Patent number: 11855035Abstract: A stack of electrical components has a first electrical component having a first surface, a second surface that is opposite to the first surface and a side surface that is located between the first surface and the second surface; a second electrical component having a third surface on which the first electrical component is mounted, the third surface facing the second surface and forming a corner portion between the third surface and the side surface; an adhesive layer that bonds the first electrical component to the second electrical component, the adhesive layer has a first portion that is located between the second and third surface and a second portion that is made of a same material as the first portion and that fills the corner portion; and a conductive layer that extends on a side of the side surface, curves along the second portion and extends to the third surface.Type: GrantFiled: June 29, 2021Date of Patent: December 26, 2023Assignee: TDK CorporationInventors: Yohei Hirota, Hiroshi Yamazaki, Hitoshi Iwama, Yusuke Takahashi
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Patent number: 11848285Abstract: A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same, the semiconductor chip including a substrate that includes a device region and an edge region; a device layer and a wiring layer that are sequentially stacked on the substrate; a subsidiary pattern on the wiring layer on the edge region; a first capping layer that covers a sidewall of the subsidiary pattern, a top surface of the wiring layer, and a sidewall of the wiring layer, the first capping layer including an upper outer sidewall and a lower outer sidewall, the lower outer sidewall being offset from the upper outer sidewall; and a buried dielectric pattern in contact with the lower outer sidewall of the first capping layer and spaced apart from the upper outer sidewall of the first capping layer.Type: GrantFiled: February 15, 2022Date of Patent: December 19, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwangwuk Park, Youngmin Lee, Inyoung Lee, Sungdong Cho
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Patent number: 11848293Abstract: A semiconductor package includes a sequential stack of first and second semiconductor chips, and a first internal connection member that connects the first and second semiconductor chips to each other. The first semiconductor chip includes a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and a first conductive pad on the first top surface. The second semiconductor chip includes a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and a second conductive bump on the second bottom surface. The first internal connection member connects the first conductive pad to the second conductive bump. The first conductive pad has a first width in one direction. The second conductive bump has a second width in the one direction. The first width is smaller than the second width.Type: GrantFiled: July 15, 2021Date of Patent: December 19, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Sunkyoung Seo, Teak Hoon Lee, Chajea Jo
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Patent number: 11842826Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.Type: GrantFiled: June 23, 2020Date of Patent: December 12, 2023Assignee: Intel CorporationInventors: Adel Elsherbini, Feras Eid, Johanna Swan, Georgios Dogiamis
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Patent number: 11843057Abstract: The present invention disclosures an oxide semiconductor transistor and a method of fabricating the same. The oxide semiconductor transistor according to an embodiment of the present invention includes a first gate electrode formed on a substrate; a first gate insulating film formed using a solution process on the first gate electrode; a source electrode and a drain electrode separately formed on one surface of the first gate insulating film; an oxide semiconductor film formed using a solution process on the first gate insulating film and the source and drain electrodes; a second gate insulating film formed using a solution process on the oxide semiconductor film; pixel electrodes separately formed on one surface of the second gate insulating film and electrically connected to the source and drain electrodes, respectively; and a second gate electrode formed on the second gate insulating film.Type: GrantFiled: July 23, 2021Date of Patent: December 12, 2023Assignee: UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITYInventors: Jin Jang, Tae Hun Kim
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Patent number: 11837568Abstract: A bonding structure is provided, wherein the bonding structure includes a first substrate, a second substrate, a first adhesive layer, a second adhesive layer, and a silver feature. The second substrate is disposed opposite to the first substrate. The first adhesive layer is disposed on the first substrate. The second adhesive layer is disposed on the second substrate and opposite the first adhesive layer. The silver feature is disposed between the first adhesive layer and the second adhesive layer. The silver feature includes a silver nano-twinned structure that includes twin boundaries that are arranged in parallel. The parallel-arranged twin boundaries include 90% or more [111] crystal orientation.Type: GrantFiled: August 27, 2021Date of Patent: December 5, 2023Assignee: AG MATERIALS TECHNOLOGY CO., LTD.Inventors: Tung-Han Chuang, Hsing-Hua Tsai
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Patent number: 11837502Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a front side of a wafer, the wafer having a plurality of dies at the front side of the wafer, the first dielectric layer having a first shrinkage ratio smaller than a first pre-determined threshold; curing the first dielectric layer at a first temperature, where after curing the first dielectric layer, a first distance between a highest point of an upper surface of the first dielectric layer and a lowest point of the upper surface of the first dielectric layer is smaller than a second pre-determined threshold; thinning the wafer from a backside of the wafer; and performing a dicing process to separate the plurality of dies into individual dies.Type: GrantFiled: June 7, 2021Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Che Tu, Wei-Chih Chen, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
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Patent number: 11830847Abstract: According to one embodiment, a manufacturing method of a semiconductor device is provided. The manufacturing method includes removing a portion of an edge region from a front surface of a first substrate to form a notch in the edge region; bonding the front surface of the first substrate and a front surface of a second substrate together to forma stacked substrate, wherein the stack substrate includes an opening at a position corresponding to the notch; and filling the opening with an embedding member.Type: GrantFiled: August 23, 2021Date of Patent: November 28, 2023Assignee: KIOXIA CORPORATIONInventor: Gen Toyota
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Patent number: 11830835Abstract: A semiconductor chip includes a chip pad arranged at a surface of the semiconductor chip. A dielectric layer is arranged at the surface of the semiconductor chip. The dielectric layer has an opening within which a contact portion of the chip pad is exposed, the opening having at least one straight side. The dielectric layer includes a solder flux outgassing trench arranged separate from and in the vicinity of the at least one straight side of the opening and that extends laterally beyond sides of the opening adjoining the straight side.Type: GrantFiled: August 17, 2021Date of Patent: November 28, 2023Assignee: Infineon Technologies AGInventors: Michael Stadler, Paul Armand Asentista Calo
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Patent number: 11832483Abstract: A display device comprises a first electrode of a (1-1)-th subpixel, a first electrode of a (1-2)-th subpixel, a first electrode of a (2-1)-th subpixel, and a first electrode of a (2-2)-th subpixel; a (1-1)-th welding electrode connected to the first electrode of the (1-1)-th subpixel, a (1-2)-th welding electrode connected to the first electrode of the (1-2)-th subpixel, a (2-1)-th welding electrode connected to the first electrode of the (2-1)-th subpixel, and a (2-2)-th welding electrode connected to the first electrode of the (2-2)-th subpixel; and a first repair line overlapping the (1-1)-th welding electrode and the (2-1)-th welding electrode and a second repair line overlapping the (1-2)-th welding electrode and the (2-2)-th welding electrode, wherein the first repair line and the second repair line are disposed on different layers with at least one insulating layer interposed therebetween.Type: GrantFiled: June 9, 2021Date of Patent: November 28, 2023Assignee: LG DISPLAY CO., LTD.Inventors: Yoohwan Kim, Sungho Cho, Hyunjae Yoo