Abstract: A memory device, a host device and a method of operating the memory device are provided. The memory device includes a data signal generator configured to provide a data signal to a transmission driver, the transmission driver configured to output a multi-level signal having any one of first to third signal levels based on the data signal, a command decoder configured to receive a feedback signal from outside of the memory device and decode the feedback signal, a data signal controller configured to adjust the data signal based on a decoding result of the command decoder, and a drive strength controller configured to adjust at least one of the first to third signal levels based on the decoding result of the command decoder.

Abstract: A computer system configured to overcome the conventional bottleneck of memory throughput. A wafer-on-wafer (WOW) technology is adapted to overcome the physical limitation of quantity and length in circuit deployments. The memory devices and the memory controllers in the logic circuit layer are improved to transmit data in differential signals. The differential signals can significantly reduce the error rate in high-speed transmissions, at a voltage level far lower than that of the conventional single-end signals. Thus, the power consumption of the computer system is significantly reduced. Furthermore, the memory controller in the computer system is improved to be an integrated controller having control over physical layer signals. Thereby, the conventional physical layer interface is no longer needed in the computer system, and therefore the cost to the computer system is further reduced.

Abstract: A method of controlling a memory device includes receiving a write instruction; starting a write operation to a first address in response to the write instruction; receiving a first read instruction of the first address; suspending the write operation; and applying a read voltage to a word line corresponding to the first address in a first read operation in response to the first read instruction. The method further includes resuming the write operation is after applying the read voltage; receiving a second read instruction after applying the read voltage; and outputting read data from a data register in response to the second read instruction during a period starting at resuming the write operation and ending at completion of the write operation.

Abstract: A modular Error Correction Code (ECC) scheme in a multi-channel IO link of an integrated circuit device is provided. The integrated circuit device may include core logic circuitry that may be configured after manufacturing. To accommodate the resulting variation, the modular ECC scheme may allow for partitioning a parity check matrix associated with the configuration of the core logic and peripheries coupled to the core logic. The parity check matrix is partitioned into smaller block matrices that is programmable. Multiple ECC modules corresponding to the block matrices are used to provide error detection and correction in the multi-channel IO link. The modular ECC scheme combined with programmable matrices (configurability) enables multi-channel IO link to be flexible to form different IO topologies.

Abstract: A ferromagnetic free layer, a preparation method and an application thereof are provided, where the ferromagnetic layer includes a magnetic film alloy, and the magnetic film alloy includes multiple layers of laminated films. A thickness of each of the films decreases gradually from a first end to a second end of the magnetic film alloy, so as to break in-plane structural symmetry of the magnetic film alloy, and the films include heavy metal films and ferromagnetic metal films, where out-of-plane crystal symmetry of the magnetic film alloy is broken by means of component gradients. When a current is applied in plane of the magnetic film alloy, a spin orbit torque will be generated, which directly drives the magnetic moment of the magnetic film alloy to undergo a deterministic magnetization reversal.

Abstract: A memory device includes a plurality of memory cells, each including a switching device and an information storage device connected to the switching device and having a phase change material, the plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a decoder circuit determining at least one of the plurality of memory cells to be a selected memory cell, and a program circuit configured to input a programming current to the selected memory cell to perform a programming operation and configured to detect a resistance of the selected memory cell to adjust a magnitude of the programming current.

Abstract: In certain aspects, a memory device includes an array of memory cells, including a first memory cell and a second memory cell, and a peripheral circuit. The peripheral circuit includes a page buffer circuit and control logic. The control logic is configured to suspend a program operation on the first memory cell responsive to receiving a suspension command, control the page buffer circuit to store suspended program information associated with a suspension of the program operation, control the page buffer circuit to release a sensing storage unit and a cache storage unit of the page buffer circuit from being occupied by the suspension of the program operation through a storage of a piece of program information from the suspended program information in a memory controller, and initiate a read operation on the second memory cell using the sensing storage unit and the cache storage unit.

Abstract: A memory device includes a memory cell array, a row select circuit, a refresh controller and a memory control logic. The memory cell array includes memory cells arranged in rows and columns. The row select circuit is connected to the rows. The refresh controller controls the row select circuit to apply a refresh operating voltage to one or more rows. The memory control logic decodes a command received from a memory controller and outputs a refresh command and external refresh address information. The refresh controller controls the row select circuit to perform one of an external refresh operation and an internal refresh operation, based on the refresh command that is output from the memory controller and based on whether a first row-hammering row address of the internal refresh operation is identical with a second row-hammering row address of the external refresh operation.

Abstract: A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. Additionally, the memory device includes a state machine configured to receive a command into a first partition of the state machine and to enable a data strobe (DQS) input buffer in response to the indication. The state machine is also configured to maintain the enablement of the DQS input buffer while the command traverses the state machine. Furthermore, the state machine is configured to disable the DQS input buffer after a set duration of time.

Abstract: A fin field-effect transistor (FinFET) based semiconductor memory array having a plurality of memory cells, each memory cell including a write transistor having a write wordline gate over a first fin connected to a write wordline gate contact, a write bitline contact in connection with the first fin, and a storage node contact in connection with the first fin, and a read transistor having a storage node gate over a second fin, the storage node gate connected to a storage node gate contact, the storage node gate contact connected to the storage node contact, a read wordline contact in connection with the second fin, and a read bitline contact in connection with the second fin, wherein the write wordline gate and the storage node gate are arranged in series to each other along an extension axis that coincides with an longitudinal axis of the write wordline gate and a longitudinal axis of the storage node gate.

Abstract: A semiconductor device includes a substrate, a first external connection pad separated from the substrate in a first direction, which is a thickness direction thereof, a first coil separated from the substrate in the first direction and electrically connected to the connection pad, a first stacked body between the connection pad and the substrate and between the first coil and the substrate, the first stacked body including a first insulator, a first wiring therein, and a first pad electrically connected to the wiring, and a second stacked body between the first stacked body and the substrate, the second stacked body including a second insulator, a second wiring therein, a second pad electrically connected to the second wiring, and a second coil. The first insulator contacts the second insulator. The first pad contacts the second pad. A part of the first coil overlaps the second coil in the first direction.

Abstract: A memory device including a memory cell array including a first sub memory cell array including a first memory cell and a second sub memory cell array including a second memory cell, a merged write driver including a first write circuit receiving n-bit data (n being a natural number ?2) through a write input/output line, outputting a first write voltage to a merged node in response to a first data bit of the n-bit data, and outputting a second write voltage to the merged node in response to a second data bit of the n-bit data, and a column decoder including a first column multiplexer applying a first voltage of the merged node corresponding to the first data bit to the first memory cell and a second column multiplexer applying a second voltage of the merged node corresponding to the second data bit to the second memory cell.

Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.

Abstract: A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells. To allow closer placement of word line switches that supply different blocks and support the possible large voltage differences between their transistors, word line switches supplying different blocks are formed over a single active region and separated by an intermediate control gate set to be off.

Abstract: A clock circuit and a memory are provided. The clock circuit includes a data strobe clock circuit and a system clock circuit. The data strobe clock circuit is configured to receive and transmit a data strobe clock signal, the data strobe clock signal is used for controlling at least one of receiving or sending of a data signal. The system clock circuit is configured to receive and transmit a system clock signal, the system clock signal is used for controlling receiving of a command signal. The system clock circuit includes at least two first signal transmission paths, and is configured to transmit the system clock signal via different first signal transmission paths in the at least two first signal transmission paths based on at least one of: different receiving rates, or different sending rates of the data signal.

Abstract: A memory device includes a memory array comprising a plurality of wordlines, and control logic, operatively coupled with the memory array. The control logic causes a measurement programming pulse to be sequentially applied to each of the plurality of wordlines of the memory array and determines respective threshold voltages stored in a number of memory cells associated with each of the plurality of wordlines. The control logic further determines a difference in the respective threshold voltages based on a location of the number of memory cells within each wordline and determines a respective resistance-capacitance (RC) time constant for each of the plurality of wordlines in view of the difference in the respective threshold voltages.

Abstract: The present disclosure includes apparatuses, methods, and systems for drift compensation for codewords in memory. An embodiment includes a memory device having an array of memory cells, and circuitry to sense a codeword stored in the array, determine a threshold voltage value of each cell of the codeword, sort the threshold voltage values, determine a second derivative value of a cell metric for a number of the cells of the codeword based on the threshold voltage value of that respective cell, the threshold voltage value immediately preceding the threshold voltage value of that respective cell in the sorted values, and a value proportional to a total quantity of the cells of the codeword, determine the cell metric for which the determined second derivative value has a greatest value, input the determined cell metric to a Pearson detector, and determine originally programmed data of the codeword using the Pearson detector.

Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with a memory device training are described. An apparatus for memory device training can include a memory device and a processing device communicatively coupled to the memory device. The processing device can be configured to perform a plurality of training rounds associated with performance of the memory device at different temperatures and different voltages and write results of the plurality of training rounds to a plurality of mode registers of the memory device. The processing device can also be configured to log an initial group identifier into a current GID MR as a reference identifier and in response to a threshold deviation from the reference ID or in response to lack of deviation outside the threshold for a threshold amount of time, retrieve an updated training setting from the results in the plurality of mode registers and enable the updated training setting.

Abstract: Memory devices are provided. In an embodiment, a memory device includes a static random access memory (SRAM) array. The SRAM array includes a static random access memory (SRAM) array. The SRAM array includes a first subarray including a plurality of first SRAM cells and a second subarray including a plurality of second SRAM cells. Each n-type transistor in the plurality of first SRAM cells includes a first work function stack and each n-type transistor in the plurality of second SRAM cells includes a second work function stack different from the first work function stack.

Abstract: Disclosed are a non-volatile memory device, a memory system including the same and a read method of the memory system, in which the non-volatile memory device includes a first storage in which a basic offset level for a read retry operation is stored, a second storage in which an additional offset level for the read retry operation is stored, and a voltage generator suitable for adjusting, when the read retry operation is performed, a read voltage by using the basic offset level and further by selectively using the additional offset level depending on a read operation.