Patents Examined by Yaima Rigol
  • Patent number: 11941254
    Abstract: A memory sub-system, such as a solid state drive (SSD), having host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands to retrieve data from the memory cells and executions the write commands to store data into the memory cells. During an autonomous self-test operation of the memory sub-system, the memory sub-system is configured to generate random challenges of proof of space, generate using a proof of space plot, stored in the memory cells, responses to the random challenges respectively, and determine validity of the responses to evaluate health of the memory cells.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Joseph Harold Steinmetz, Luca Bert
  • Patent number: 11941285
    Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, receiving a read request to perform a read operation on a block of the memory device; determining whether an entry corresponding to the block is stored in a data structure associated with the memory device; responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device; resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since the read operation was performed on the block of the memory device; determining that the counter and the timer satisfy a first criterion; and responsive to determining that the counter and the timer satisfy the first criterion, removing the entry corresponding to the block from the data structure associated with the memory device.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Ashutosh Malshe, Giuseppina Puzzilli, Saeed Sharifi Tehrani
  • Patent number: 11934669
    Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: March 19, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dimin Niu, Shuangchen Li, Bob Brennan, Krishna T. Malladi, Hongzhong Zheng
  • Patent number: 11934667
    Abstract: Techniques for encrypted-data-only media operations are described. In some instances, data from a source to be written to memory of a storage device is received by a storage device and the storage devices determines whether the data is encrypted at a storage location based on an amount of entropy of the received data. When the received data is not encrypted a media error is returned to the source and when the received data is encrypted the data is written.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: March 19, 2024
    Assignee: Amazon Technologies, Inc.
    Inventor: Rodrigo Rubira Branco
  • Patent number: 11914860
    Abstract: A processor receives, from an input device, input data for processing. Upon determining that the input data corresponds to an artificial intelligence (AI) application, the processor generates an AI command for performing read or write operations for a memory device that is configured to store data for a plurality of applications including the AI application, the AI command characterized by an operational code and including information about one or more components of the AI application corresponding to the input data. The processor sends the AI command and the input data to a storage controller managing the memory device, wherein the read or write operations for the memory device are performed by the storage controller using the operational code and the information included in the AI command. The processor receives, from the storage controller, a result of the read or write operations performed on the memory device.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 27, 2024
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hung Lai, Hung-Sheng Chang
  • Patent number: 11914516
    Abstract: System and techniques for memory side cache request handling are described herein. When a memory request is received, a cache set for the memory request is determined. Here, the cache set has multiple ways and each way corresponds to a cache line. It can be detected that a way of the multiple ways is not ready for the memory request. In this case, a representation of the memory request is stored in a queue of multiple queues based on an interface upon which the memory request was received and the present ways of the cache set. Entries from the multiple queues can be dequeued in a defined order to determine a next memory request to process. The defined order gives priority to memory requests for a present way and then for external over internal requests.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Dean E. Walker, Tony M. Brewer
  • Patent number: 11907585
    Abstract: A method for execution by a storage unit in a dispersed storage network (DSN) includes selecting a storage zone of a memory device of the storage unit based on zone allocation parameters, and designating the selected storage zone as open for writes. A data slice is received via a network for storage. The data slice is written sequentially at a memory location of the one of storage zone based on determining that the storage zone is designated as open for writes. A pointer corresponding to the data slice that indicates the storage zone and the memory location is generated. A read request is received via the network from a requesting entity that indicates the data slice. The data slice is retrieved from the memory device based on the pointer, and is transmitted to the requesting entity.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: February 20, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew D. Baptist, Manish Motwani, Praveen Viraraghavan, Ilya Volvovski
  • Patent number: 11907127
    Abstract: In certain aspects, one or more solid-state storage devices (SSDs) are provided that include a controller and non-volatile memory coupled to the controller. The non-volatile memory can include one or more portions configured as main memory or cache memory. When data stored in the main memory is written to the cache memory for processing, the data in the main memory is erased. In certain aspects, storage systems are provided that include one or more of such SSDs coupled to a host system. In certain aspects, methods are provided that include: receiving, by a first such SSD, a first command to write data to memory; determining that the data is stored in a main memory and is to be written to the cache memory for processing; writing the data to the cache memory; and erasing the data from the main memory.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: February 20, 2024
    Assignee: SMART IOPS, INC.
    Inventors: Ashutosh Kumar Das, Manuel Antonio d'Abreu
  • Patent number: 11907588
    Abstract: Aspects of the invention include identifying a first subsystem and a second subsystem of a plurality of subsystems respectively storing a first compressed data and a second compressed data, wherein the first compressed data and the second compressed data are fragments of a requested data. A compression method used to compress the first compressed data and second compressed data is identified. A first accelerator of first subsystem and a second accelerator of the second subsystem is identified. The first compressed data from a first local memory of the first subsystem is offloaded to the first accelerator, and the second compressed data from a second local memory of the second subsystem is offloaded to the second accelerator, wherein offloading comprises provided a decompression method for the first compressed data and the second compressed data.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: February 20, 2024
    Assignee: International Business Machines Corporation
    Inventors: Vishnupriya R, Mehulkumar J. Patel, Manish Mukul
  • Patent number: 11892953
    Abstract: An interprocess communication (IPC) method and an IPC system for transmit communication data from a first process to a second process, where the method includes performing initialization configuration on the first process and the second process, including creating first memory space in shared memory space, selecting a communication manner based on a length of the communication data and a value of a threshold, where the threshold is a size of the first memory space, performing interprocess data exchange in the selected communication manner, selecting a memory sharing manner for communication when the length of the communication data is less than the threshold, and selecting a data file manner for communication when the length of the communication data reaches or exceeds the threshold.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: February 6, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Qibin Yang, Senyu Liu, Xiaohui Bie
  • Patent number: 11893248
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command from a host device to read data from the memory device, fetch the read data from the memory device, check metadata associated with the read data, determine if the metadata corresponds to the read command, and provide modified read data to the host device when the metadata does not correspond to the read command. The modified read data may be encrypted read data, corrupted read data, or read data that is replaced with debug information. When the host device receives data that is different than the read data that is requested, the modified read data may be unreadable to the host device so that unprivileged access to the read data may be avoided.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amir Segev, Shay Benisty
  • Patent number: 11893251
    Abstract: A non-transitory computer-readable medium is disclosed, the medium having instructions stored thereon that are executable by a computer system to perform operations that may include allocating a plurality of storage locations in a system memory of the computer system to a buffer. The operations may further include selecting a particular order for allocating the plurality of storage locations into a cache memory circuit. This particular order may increase a uniformity of cache miss rates in comparison to a linear order. The operations may also include caching subsets of the plurality of storage locations of the buffer using the particular order.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 6, 2024
    Assignee: Apple Inc.
    Inventors: Rohit Natarajan, Jurgen M. Schulz, Christopher D. Shuler, Rohit K. Gupta, Thomas T. Zou, Srinivasa Rangan Sridharan
  • Patent number: 11880596
    Abstract: According to one embodiment, a storage system includes a network interface controller, a volatile memory and a storage device. The network interface controller is configured to communicate with a client using remote direct memory access. The network interface controller is configured to store write data and a submission queue entry including a write request of the write data transferred using the remote direct memory access in the volatile memory. The storage device is configured to write, when the submission queue entry is stored in a submission queue of the volatile memory, the write data to the storage device based on the submission queue entry.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: January 23, 2024
    Assignee: Kioxia Corporation
    Inventors: Shintaro Sano, Kazuhiro Hiwada
  • Patent number: 11880578
    Abstract: Techniques are provided for providing a storage abstraction layer for a composite aggregate architecture. A storage abstraction layer is utilized as an indirection layer between a file system and a storage environment. The storage abstraction layer obtains characteristic of a plurality of storage providers that provide access to heterogeneous types of storage of the storage environment (e.g., solid state storage, high availability storage, object storage, hard disk drive storage, etc.). The storage abstraction layer generates storage bins to manage storage of each storage provider. The storage abstraction layer generates a storage aggregate from the heterogeneous types of storage as a single storage container. The storage aggregate is exposed to the file system as the single storage container that abstracts away from the file system the management and physical storage details of data of the storage aggregate.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: January 23, 2024
    Assignee: NetApp, Inc.
    Inventors: Ananthan Subramanian, Sriram Venketaraman, Ravikanth Dronamraju, Mohit Gupta
  • Patent number: 11868778
    Abstract: Compacted addressing for transaction layer packets, including: determining, for a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing, from one or more memory addresses of one or more second transaction layer packets, the one or more low entropy address bits; and sending the one or more second transaction layer packets.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: January 9, 2024
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Ganesh Dasika, Sergey Blagodurov, Seyedmohammad Seyedzadehdelcheh
  • Patent number: 11860773
    Abstract: Systems, apparatuses, and methods related to memory access statistics monitoring are described. A host is configured to map pages of memory for applications to a number of memory devices coupled thereto. A first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. A second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. The host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventor: David A. Roberts
  • Patent number: 11860669
    Abstract: The invention introduces a method, an apparatus and a non-transitory computer program product for storing data in flash memory. The method is performed by a processing unit when loading and executing program code of a flash translation layer to include: dividing storage space of a flash module into a first region and a second region; programming data belonging to a first partition type received from a host side into first physical blocks of the first region only; and programming data belonging to a second partition type received from the host side into the first physical blocks of the first region and the second physical blocks of the second region. With the region division and the policy for writing data into the regions in terms of data characteristics of different partition types, storage space of the flash module would be used more effective.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: January 2, 2024
    Assignee: SILICON MOTION, INC.
    Inventor: Kuan-Yu Ke
  • Patent number: 11847465
    Abstract: Disclosed is a parallel processor. The parallel processor includes a processing element array including a plurality of processing elements arranged in rows and columns, a row memory group including row memories corresponding to rows of the processing elements, a column memory group including column memories corresponding to columns of the processing elements, and a controller to generate a first address and a second address, to send the first address to the row memory group, and to send the second address to the column memory group. The controller supports convolution operations having mutually different forms, by changing a scheme of generating the first address.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: December 19, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chun-Gi Lyuh, Hyun Mi Kim, Young-Su Kwon, Jin Ho Han
  • Patent number: 11836083
    Abstract: A compute node includes a memory, a processor and a peripheral device. The memory is to store memory pages. The processor is to run software that accesses the memory, and to identify one or more first memory pages that are accessed by the software in the memory. The peripheral device is to directly access one or more second memory pages in the memory of the compute node using Direct Memory Access (DMA), and to notify the processor of the second memory pages that are accessed using DMA. The processor is further to maintain a data structure that tracks both (i) the first memory pages as identified by the processor and (ii) the second memory pages as notified by the peripheral device.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: December 5, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Ran Avraham Koren, Ariel Shahar, Liran Liss, Gabi Liron, Aviad Shaul Yehezkel
  • Patent number: 11822827
    Abstract: Embodiments disclosed herein provide systems, methods, and computer readable media for sub-cluster recovery in a data storage environment having a plurality of storage nodes. In a particular embodiment, the method provides scanning data items in the plurality of nodes. While scanning, the method further provides indexing the data items into an index of a plurality of partition groups. Each partition group includes data items owned by a particular one of the plurality of storage nodes. The method then provides storing the index.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: November 21, 2023
    Assignee: Rubrik, Inc.
    Inventors: Rohit Shekhar, Hyo Jun Kim, Prasenjit Sarkar, Maohua Lu, Ajaykrishna Raghavan, Pin Zhou